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FEATURES

TERMINAL ASSIGNMENT

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20

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S0/A0/CLK_SEL

S1/A1

GND

CLK_IN0

CLK_IN1

GND

SDATA

SCLOCK

Y5

Y4

GND

Y3

Y2

GND

Y1

Y0

PW PACKAGE

(TOP VIEW)

TSSOP 20

Pitch 0,65 mm

6.6 x 6.6

DESCRIPTION

CDCE706

SCAS815A – OCTOBER 2005 – REVISED OCTOBER 2005

PROGRAMMABLE 3-PLL CLOCK SYNTHESIZER / MULTIPLIER / DIVIDER

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Separate Power Supplies for Outputs (2.3 V to

3.6 V) Supports Mixed Power Supply

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High Performance 2:6 PLL based Clock

Environments

Synthesizer / Multiplier / Divider

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3.3-V Device Power Supply

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User Programmable PLL Frequencies using

EEPROM Technology

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Industrial Temperature Range –40

°C to 85°C

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EEPROM Programming Without the Need to

•

Development and Programming Kit for Ease

Apply High Programming Voltage

PLL Design and Programming (TI

Pro-Clock™)

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Easy In-Circuit Programming via SMBus Data

Interface

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Packaged in 20-Pin TSSOP

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Wide PLL Divider Ratio Allows 0-ppm Output

Clock Error

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Clock Inputs Accept a Crystal or a

Single-Ended LVCMOS or a Differential Input

Signal

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Accepts Crystal Frequencies from 8 MHz up

to 54 MHz

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Accepts LVCMOS or Differential Input

Frequencies up to 200 MHz

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Two Programmable Control Inputs [S0/S1,

A0/A1] for User Defined Control Signals

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Six LVCMOS Outputs with Output

Frequencies up to 300 MHz

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LVCMOS Outputs can be Programmed for

Complementary Signals (Pseudo Differential

Outputs)

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Free Selectable Output Frequency via

Programmable Output Switching Matrix [6x6]

Including 7-Bit Post-Divider for Each Output

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PLL Loop Filter Components Integrated

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Low Period Jitter (Typ 60 ps)

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Features Spread Spectrum Clocking (SSC) for

Lowering System EMI

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Programmable Output Slew-Rate Control

(SRC) for Lowering System EMI

The CDCE706 is one of the smallest and powerful PLL synthesizer / multiplier / divider available today. Despite

its small physical outlines, the CDCE706 is the most flexible. It has the capability to produce an almost

independent output frequency from a given input frequency.

The input frequency can be derived from a LVCMOS, differential input clock, or a single crystal. The appropriate

input waveform can be selected via the SMBus data interface controller.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Pro-Clock is a trademark of Texas Instruments.

PRODUCT PREVIEW information concerns products in the

Copyright © 2005, Texas Instruments Incorporated

formative or design phase of development. Characteristic data and

other specifications are design goals. Texas Instruments reserves

the right to change or discontinue these products without notice.