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CDCE706

SCAS815A – OCTOBER 2005 – REVISED OCTOBER 2005

Byte 19 to 24, Bit [3]: Output Y0-Y5 Enable or Low-State

ENDISYx

Output Yx

0

Disable to low

1

Enable

Yes

(1)

Unless customer specific setting.

Byte 19 to 24, Bit [6]: Output Y0-Y5 Non-Inverting/Inverting

INVYx

Output Yx Status

0

Non-inverting

Yes

1

Inverting

(1)

Unless customer specific setting.

EEPIP

Indicate EEPROM Write Process

Default

0

No programming

1

Programming in process

(1)

This read only Bit indicates an EEPROM write process. It is set to high if programming starts and resets to low if programming is

completed. Any data written to the EEPIP-Bit will be ignored. During programming, no data are allowed to be sent to the device via the

SMBus until the programming sequence is completed. Data, however, can be readout during the programming sequence (Byte Read or

Block Read).

FSSC3

FSSC2

FSSC1

FSSC0

Modulation

Factor

100

110

120

130

140

150

160

167

0

0

0

0

5680

17.6

19.4

21.1

22.9

24.6

26.4

28.2

29.4

[kHz]

0

0

0

1

5412

18.5

20.3

22.2

24.0

25.9

27.7

29.6

30.9

0

0

1

0

5144

19.4

21.4

23.3

25.3

27.2

29.2

31.1

32.5

0

0

1

1

4876

20.5

22.6

24.6

26.7

28.7

30.8

32.8

34.2

0

1

0

0

4608

21.7

23.9

26.0

28.2

30.4

32.6

34.7

36.2

0

1

0

1

4340

23.0

25.3

27.6

30.0

32.3

34.6

36.9

38.5

0

1

1

0

4072

24.6

27.0

29.5

31.9

34.4

36.8

39.3

41.0

0

1

1

1

3804

26.3

28.9

31.5

34.2

36.8

39.4

42.1

43.9

1

0

0

0

3536

28.3

31.1

33.9

36.8

39.6

42.4

45.2

47.2

1

0

0

1

3286

30.4

33.5

36.5

39.6

42.6

45.6

48.7

50.8

Yes

1

0

1

0

3000

33.3

36.7

40.0

43.3

46.7

50.0

53.3

55.7

1

0

1

1

2732

36.6

40.3

43.9

47.6

51.2

54.9

58.6

61.1

1

1

0

0

2464

40.6

44.6

48.7

52.8

56.8

60.9

64.9

67.8

1

1

0

1

2196

45.5

50.1

54.6

59.2

63.8

68.3

72.9

76.0

1

1

1

0

1928

51.9

57.1

62.2

67.4

72.6

77.8

83.0

86.6

1

1

1

1

1660

60.2

66.3

72.3

78.3

84.3

90.4

96.4

100.6

(1)

The PLL has to be bypassed (turned off) when changing SSC Modulation Frequency Factor on-the-fly. This can be done by following

programming sequence: bypass PLL2 (Byte 3, Bit 6 = 1); write new Modulation Factor (Byte 25); re-activate PLL2 (Byte 3, Bit 6 = 0).

(2)

Unless customer specific setting.

SSC2

SSC1

SSC0

Function

0

0

0

0

0

1

SSC Modulation Amount

±0.1% (center spread)

0

1

0

SSC Modulation Amount

±0.25% (center spread)

0

1

1

SSC Modulation Amount

±0.4% (center spread)

1

0

0

SSC Modulation Amount 1% (down spread)

Yes

(1)

The PLL has to be bypassed (turned off) when changing SSC Modulation Amount on-the-fly. This can be done by following

programming sequence: bypass PLL2 (Byte 3, Bit 6 = 1); write new Modulation Amount (Byte 25); re-activate PLL2 (Byte 3, Bit 6 = 0).

(2)

Unless customer specific setting.

(3)

If SSC bypass is selected, SSC circuitry of PLL2 is powered-down and the SSC output is reset to logic low. The non-SSC output of

PLL2 is not affected by this mode and can still be used.

17