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Multi-Function Control Inputs S0 and S1

Output Switching Matrix

CDCE706

SCAS815A – OCTOBER 2005 – REVISED OCTOBER 2005

The CDCE706 features two user definable inputs pins which can be used as external control pins or address

pins. When programmed as control pins, they can function as clock select pin, enable/disable pin or device

power-down pin. If both pins used as address-bits, up to four devices can be connected to the same SMBus. The

respective function is set in Byte 10; Bit [3:0]. Table 4 shows the possible setting for the different output

conditions, clock select and device addresses.

Table 4. Configuration Setting of Control Inputs

Configuration Bits

External Control Pins

Device Function

Byte 10,

Byte 10,

Bit [3:2]

Bit [1:0]

S11

S10

S01

S00

S1

S0

Yx Outputs

Power

Pin 2

Pin 1

(Pin 2)

(Pin 1)

Down

0

X

0

X

1

1

Active

No

Output ctrl

Output ctrl

0

0

0

X

0

1

No

Output ctrl

Output ctrl

0

1

0

X

0

1

3-State

Outputs only

Output ctrl

Output ctrl

0

X

0

0

X

0

3-State

PLL, inputs and outputs

Output ctrl

Output ctrl and pd

0

X

0

1

0

0

PLL only

Output ctrl

PLL and Div bypass

S10=1: 3-State

0

X

0

1

1

0

Active

PLL only

Output ctrl

PLL and Div bypass

0

X

1

0

0

No

Output ctrl

CLK_SEL

S10=1: 3-State

0

X

1

0

1

Active

No

Output ctrl

CLK_SEL

1

1

1

1

X

X

Active

No

(1)

A non-inverting output will be set to low and an inverting output will be set to high.

(2)

If S0 is 0, CLK_IN0 is selected; if S0 is 1, CLK_IN1 is selected.

(3)

S0 and S1 are interpreted as Address Bit A0 and A1 of the Slave Receiver Address Byte.

As shown in Table 4, there is a specific order of the different output condition: Power-down mode overwrites

3-state, 3-state overwrites low-state, and low-state overwrites active-state.

The flexible architecture of the output switch matrix allows the user to switch any of the internal clock signal

sources via a free-selectable post-divider to any of the six outputs.

As shown in Figure 18, the CDCE706 is based on two banks of switches and six post-dividers. Switch A

comprises six 5-Input-Muxes which selects one of the four PLL clock outputs or directly selects the input clock

and feed it to one of the 7-bit post-divider (P-Divider). Switch B is made up of six 6-Input-Muxes which takes any

post-divider and feeds it to one of the six outputs, Yx.

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