ATMEGA640 datasheet(134/436 Pages) MICROCHIP

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ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]

DS40002211A

Figure 17-1. 16-bit Timer/Counter Block Diagram(1)

Note:

1. Refer to Figure 1-1 on page 2, Table 13-5 on page 76, and Table 13-11 on page 80 for Timer/Counter1 and 3 and

3 pin placement and description.

17.2.1

Registers

The Timer/Counter (TCNTn), Output Compare Registers (OCRnA/B/C), and Input Capture Register (ICRn) are all

16-bit registers. Special procedures must be followed when accessing the 16-bit registers. These procedures are

described in the section “Accessing 16-bit Registers” on page 135. The Timer/Counter Control Registers

(TCCRnA/B/C) are 8-bit registers and have no CPU access restrictions. Interrupt requests (shorten as Int.Req.)

signals are all visible in the Timer Interrupt Flag Register (TIFRn). All interrupts are individually masked with the

Timer Interrupt Mask Register (TIMSKn). TIFRn and TIMSKn are not shown in the figure since these registers are

shared by other timer units.

The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on the Tn pin. The

Clock Select logic block controls which clock source and edge the Timer/Counter uses to increment (or decrement)

ICFn (Int.Req.)

TOVn

(Int.Req.)

Clock Select

Timer/Counter

ICRn

TCNTn

Waveform

Generation

Waveform

Generation

Waveform

Generation

OCnA

OCnB

OCnC

Noise

Canceler

ICPn

Fixed

TOP

Values

Edge

Detector

Control Logic

= 0

TOP

BOTTOM

Count

Clear

Direction

OCFnA

(Int.Req.)

OCFnB

(Int.Req.)

OCFnC

(Int.Req.)

TCCRnA

TCCRnB

TCCRnC

( From Analog

Comparator Ouput )

Edge

Detector

( From Prescaler )

TCLK

OCRnC

OCRnB

OCRnA

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