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ATMEGA640 датащи(PDF) 133 Page - Microchip Technology |
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ATMEGA640 датащи(HTML) 133 Page - Microchip Technology |
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133 / 436 page ![]() 133 ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET] DS40002211A 17. 16-bit Timer/Counter (Timer/Counter 1, 3, 4, and 5) 17.1 Features • True 16-bit Design (that is, allows 16-bit PWM) • Three independent Output Compare Units • Double Buffered Output Compare Registers • One Input Capture Unit • Input Capture Noise Canceler • Clear Timer on Compare Match (Auto Reload) • Glitch-free, Phase Correct Pulse Width Modulator (PWM) • Variable PWM Period • Frequency Generator • External Event Counter • Twenty independent interrupt sources (TOV1, OCF1A, OCF1B, OCF1C, ICF1, TOV3, OCF3A, OCF3B, OCF3C, ICF3, TOV4, OCF4A, OCF4B, OCF4C, ICF4, TOV5, OCF5A, OCF5B, OCF5C, and ICF5) 17.2 Overview The 16-bit Timer/Counter unit allows accurate program execution timing (event management), wave generation, and signal timing measurement. Most register and bit references in this section are written in general form. A lower case “n” replaces the Timer/Counter number, and a lower case “x” replaces the Output Compare unit channel. However, when using the register or bit defines in a program, the precise form must be used, that is, TCNT1 for accessing Timer/Counter1 counter value and so on. A simplified block diagram of the 16-bit Timer/Counter is shown in Figure 17-1 on page 134. For the actual place- ment of I/O pins, see “TQFP-pinout ATmega640/1280/2560” on page 2 and “Pinout ATmega1281/2561” on page 4. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Regis- ter and bit locations are listed in the “Register Description” on page 154. The Power Reduction Timer/Counter1 bit, PRTIM1, in “PRR0 – Power Reduction Register 0” on page 55 must be written to zero to enable Timer/Counter1 module. The Power Reduction Timer/Counter3 bit, PRTIM3, in “PRR1 – Power Reduction Register 1” on page 56 must be written to zero to enable Timer/Counter3 module. The Power Reduction Timer/Counter4 bit, PRTIM4, in “PRR1 – Power Reduction Register 1” on page 56 must be written to zero to enable Timer/Counter4 module. The Power Reduction Timer/Counter5 bit, PRTIM5, in “PRR1 – Power Reduction Register 1” on page 56 must be written to zero to enable Timer/Counter5 module. Timer/Counter4 and Timer/Counter5 only have full functionality in the ATmega640/1280/2560. Input capture and output compare are not available in the ATmega1281/2561. |
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