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L99LD02 датащи(PDF) 40 Page - STMicroelectronics |
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L99LD02 датащи(HTML) 40 Page - STMicroelectronics |
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40 / 66 page ![]() Serial peripheral interface (ST SPI standard) L99LD02 40/66 DS12448 Rev 3 CR#3: Control Register 3 Address: 0x03h Type: R/W 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Unused BST_OUT_FAIL_FilterTime BST_FREQ Table 24. CR#3: Control Register 3 Bit Default Name Description 23÷16 Unused 15÷13 DEF_BOF_FT(000) BST_OUT_FAIL_FilterTim e Filtering time before setting the boost output failure bit. It takes effect after boost_power_good signal is “1” for the first time The boost out fail filtering time shall be configurable in 8 steps: 000 --> 500µs 001 --> 10µs 010 --> 50µs 011 --> 100µs 100 --> 300µs 101 --> 800µs 110 --> 1000µs 111 --> 2000µs 12 DEF_DITH_EN(0) DITH_EN Dithering enable: enable or disable random dither effect. If this bit is set Dithering is enabled; If the bit is reset, the dithering is disabled 11÷10 DEF_BST_FDEV(00) BST_FDEV Boost clock frequency deviation The clock frequency deviation shall be configurable in 4 steps: 00 --> 5% 01 --> 10% 10 --> 15% 11 --> 20% 9÷8 DEF_BST_FMOD(11) BST_FMOD Boost clock frequency modulation The clock frequency modulation shall be configurable in 4 steps: 00 --> 1.95 kHz 01 --> 3.90 kHz 10 --> 7.80 kHz 11 --> 15.6 kHz |
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