L99LD02 datasheet(20/66 Pages) STMICROELECTRONICS

20 / 66 page

Boost controller

L99LD02

20/66

DS12448 Rev 3

Table 6. Clock distribution - MASTER (internal clock source)

SPI configuration

Master device

Slave device

MS (1 bit)

BST_N_PHASE (2 bits)

3 or 4 phase

Any value (this setting has no effect

in slave mode)

BST_GM_OTA (2 bits)

According to application

conditions

(see Section 3.7: Stability –

Error Amplifier characteristics)

Disabled

Enable is also allowed – then the

resulting Gm value is a sum of Gm

values of both devices. However, in

case the slave device is disabled

(e.g. due to lower output power

demand) the Gm of only master

device becomes too low with given

compensation network. This would

results in much lower regulation loop

bandwidth than it could be. Then,

another SPI command for increasing

master’s Gm value might be

needed.

BST_SLP_CTRL (6 bits)

According to application

conditions

(see Section 3.7: Stability –

Error Amplifier characteristics)

Identical as master

(is a must for equal current

balancing)

BST_OCP_LIM (2 bits)

According to application

conditions

(see CR#2 Bit[13:12],

BST_OCP_LIM in Table 23:

CR#2: Control Register 2)

Identical as master

(for consistent overcurrent

protection level)

BST_OUT (7 bits)

According to requested output

voltage

Identical as master

(for consistent overvoltage

diagnostic feedback, power good

flag and correct output voltage in

case of slave’s OTA kept enabled)

BST_DIS (2 bit)

Phase 1, Phase 2 enabled

(see CR#3 Bit[2:1], BST_DIS

in Table 24: CR#3: Control

3-phase configuration: Phase 1

enabled, Phase 2 disabled

4-phase configuration: Phase 1,

Phase 2 enabled

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