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L99LD02 датащи(PDF) 25 Page - STMicroelectronics |
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L99LD02 датащи(HTML) 25 Page - STMicroelectronics |
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25 / 66 page ![]() DS12448 Rev 3 25/66 L99LD02 Functional description 64 4.1.4 Limp Home / Stand-alone mode The device enters Limp Home automatically 400 ns after Reset mode. Limp Home characteristics are: Boost active Operation according to OTP settings SPI active: – All SPI write operations must be allowed without any effects on the device behavior. When the device leaves this mode, it can enter Standby or Active mode. If the Microcontroller sends the following SPI frames sequence: The first SPI frame sets UNLOCK bit = 1 (see bit <1> on Table 22: CR#1: Control Register 1) The second consecutive SPI frame sets GO_STBY bit = 1 and EN bit = 0, (see bit <3> and bit <2> on Table 23: CR#2: Control Register 2) Or, if in stand-alone operation, upon the condition of TM pin is low for more than a fixed time window (tTM_LOW), the device enters Pre-Standby mode. Then, the device automatically enters: Standby, if CSN high for a time t > tSTDBY; Reset, if CSN Low for a time t > tPRE_STDBY; If the Microcontroller sends to the device the sequence of the following SPI frames: The first SPI frame reads and clears the WD-Fail bit (see bit <14> on Table 26: SR#1: Status Register 1) The second SPI frame sets UNLOCK bit = 1 (see bit <1> on Table 22: CR#1: Control Register 1) The third consecutive SPI frame sets GOSTBY bit = 0 and EN bit = 1 (see bit <3> and bit <2> on Table 23: CR#2: Control Register 2) The device enters Active mode. In Limp Home, after setting bit 27 on GSB (FE1, functional error bit), an auto-restart procedure is implemented: every tAUTORESTART, functional error bit eventually set is automatically cleared. 4.1.5 Active mode The device enters the Active mode if the Microcontroller sends the following SPI frames sequence: The first SPI frame reads and clears the WD-Fail bit (see bit <14> on Table 26: SR#1: Status Register 1) The second SPI frame sets UNLOCK bit = 1 (see bit <1> on Table 22: CR#1: Control Register 1) The third consecutive SPI frame sets GOSTBY bit = 0 and EN bit = 1 (see bit <3> and bit <2> on Table 23: CR#2: Control Register 2) |
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