L99LD02 datasheet(46/66 Pages) STMICROELECTRONICS

46 / 66 page

Serial peripheral interface (ST SPI standard)

L99LD02

46/66

DS12448 Rev 3

BST_OUT_FAIL

BST_OUT pin failure.

This bit is set when BST_OUT pin is floating or shorted to

ground.

When this bit is set:

- if Boost is in off-state, then it will not be allowed to start

up;

- if Boost is in on-state, then it will immediately switched

OFF;

- in both cases, no clock is delivered through SYNC_IO

pin;

- in Limp Home, COMP pin will be pulled down.

IF BST_DIS =1, BST_OUT_FAIL bit will not be set.

When BST_OUT_FAIL = 1, Boost is disabled until a read

and clear command of this bit has been acknowledged.

In Limp Home, an auto restart procedure cyclically clears

BST_OUT_FAIL bit with a period equal to tAUTORESTART.

R/C

Unused

BST2_OCP_LIM

Overcurrent limit status bit

[0]: BST2_OCP_LIM limit is not reached or continuous

time is less than 2ms.

[1]: If BST2_OCP_LIM limit is reached during a filtering

time of typically 2ms.

– Once BST2_OCP_LIM is reached for the first time an

internal flag is set.

– This internal flag is re-evaluated cycle by cycle and is

going to be reset upon the condition that three

consecutive switching cycles have not reached

BST2_OCP_LIM threshold.

– If the internal flag is still set after elapse of typically 2ms

filtering time, the BST2_OCP_LIM status bit accessible

in the diagnostic status registers is set and latched.

R/C

BST1_OCP_LIM

Overcurrent limit status bit

[0]: BST1_OCP_LIM limit is not reached or continuous

time is less than 2ms.

[1]: If BST1_OCP_LIM limit is reached during a filtering

time of typically 2ms.

– Once BST1_OCP_LIM is reached for the first time an

internal flag is set.

– This internal flag is re-evaluated cycle by cycle and is

going to be reset upon the condition that three

consecutive switching cycles have not reached

BST1_OCP_LIM threshold.

– If the internal flag is still set after elapse of typically 2ms

filtering time, the BST1_OCP_LIM status bit accessible

in the diagnostic status registers is set and latched.

R/C

Table 26. SR#1: Status Register 1 (continued)

Bit

Defaul

Name

Description

Acces

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