Interleaved Inverting Charge Pump with

Negative LDO Regulator

Data Sheet

ADP5600

Rev. 0

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FEATURES

Input voltage: 2.7 V to 16 V

Maximum output current: −100 mA

Integrated power MOSFETs

Four LDO selectable output voltage options

−0.505 V, −1.5 V, −2.5 V, −5 V

Programmable charge pump switching frequency range

100 kHz to 1 MHz

Frequency synchronization via SYNC pin

Precision enable and power good

Internal soft start

Output short-circuit and overload protection

Shorted charge pump fly capacitor protection

Integrated LDO output discharge resistor

16-lead, 4 mm × 4 mm LFCSP

APPLICATIONS

Powering the negative rail on bipolar/split supply

ADC/DAC/AMP/mux applications

TYPICAL APPLICATIONS CIRCUITS

GENERAL DESCRIPTION

The ADP5600 is an interleaved charge pump inverter with an

integrated, negative, low dropout (LDO) linear regulator. The

interleaved charge pump inverter exhibits reduced output voltage

ripple and reflected input current noise over conventional inductive

or conventional capacitive based solutions. The integrated LDO

provides a rail with good regulation at sufficient power supply

rejection ratio (PSRR).

The ADP5600 charge pump operates via resistor programming or

external clock synchronization at switching frequency range of

100 kHz to 1 MHz. Operating at a higher switching frequency

allows the use of small input, output, and fly capacitors. To combine

the high switching frequency with internal field effect transistors

(FETs), compensation, and soft start gives a best-in-class total

solution size for negative rail generation.

The ADP5600 also features comprehensive fault protection for

robust applications. These protections include overload protection,

shorted fly capacitor protection, undervoltage lockout (UVLO),

and thermal shutdown. For easy sequencing, the ADP5600 has a

power-good pin.

The integrated LDO of the ADP5600 uses an advanced proprie-

tary architecture to provide high power supply rejection. It also

achieves decent line and load transient response with only a small

2.2 μF ceramic output capacitor. The output can be configured

via the SEL1 and SEL2 pins to one of four fixed output voltages and

feedback divider.

EN

SYNC

FREQ

SEL1

1

10kΩ

SEL2

PGOOD

GND

10kΩ

C1+

ADP5600

C1–

C2+

C2–

CPOUT

CPOUT

LDO_OUT

FB

ON

OFF

VIN

EN

SYNC

FREQ

SEL1

1

10kΩ

SEL2

PGOOD

GND

10kΩ

100kΩ

49.9kΩ

C1+

ADP5600

C1–

C2+

C2–

CPOUT

CPOUT

LDO_OUT

FB

ON

OFF

VIN