Silicon Errata for the MSC8101 Processor, Mask 0K40A, Rev. 5

20

Freescale Semiconductor

CPM73

SI RAM Corruption

Date Added: 8/5/2001

Description: (7049)An access to the SI RAM bank from the 60x bus while the corresponding

TDM is active may result in data corruption within the SI RAM.

Workaround: Associate the SI RAM bank with an inactive TDM before attempting to access

it. Once the accesses has been made, the SI RAM bank should be re-assigned to the active TDM.

System Number: 7049

Fix Plan: Rev A

0K40A

CPM74

FCC HDLC Controller Stops Transmitting When Using Nibble Mode With MFF=0

Date Added: 8/27/2001

Description: When running an FCC in HDLC nibble mode with the multi-frame per FIFO bit off

(MFF=0) the CPM may lose synchronization with the FCC HDLC controller. As a result the

HDLC controller will get stuck and stop transmission.

Workaround: When running the FCC in HDLC nibble mode set the MFF=1 or alternatively run

the FCC in HDLC bit mode.

Fix Plan: RevA

0K40A

CPM76

First transmitted bit zero in FCC Transparent Mode with GFMR[CTSS]=1

Date Added: 8/27/2001

Description: When using an FCC in transparent mode the first bit of a frame is transmitted as

zero every time RTS is asserted before CTS is asserted when CTS is sampled synchronously with

data (GFMR[CTSS]=1). If CTS is in pulse mode (GFMR[CTSP]=1) only the first frame is affect-

ed because CTS is ignored thereafter. If CTS is not in pulse mode (GFMR[CTSP]=0) then every

frame is affected separately.

Workaround: If the receiver synchronizes on a 8/16-bit sync pattern stored in the FDSR register

(GFMR[SYNL]=1x) ensure that the synchronization pattern starts with a “0”. If no synchroniza-

tion pattern is used (GRMR[SYNL]=0x) add a one-byte dummy buffer before sending the real

data buffers.

Fix Plan: RevA

0K40A

CPM79

FCC Fast Ethernet Flow Control

Date Added: 3/14/2002

Description: When the FCC receives a flow control pause message with MAC parameter

=0xffff, it sets a zero delay instead of maximum delay.

Fix Plan: RevA

0K40A

CPM80

MCC CES User Template

Date Added: 3/14/2002

Description: If the transparent MCC Tx CES channel requires the user template

(CHAMR[UTM]=1) only the first 8 bytes of the user defined pattern are transmitted. Then the

transmitter will continue to send bytes 4-7 of the pattern continuously until the counter reaches 0.

Any bytes defined in the pattern after byte 7 are never transmitted.

Workaround: Use a template size of 8 bytes.

Fix Plan: RevA

0K40A

CPM85

Only One BSY Interrupt Generated for AAL0

Date Added: 5/21/2002

Description: When using AAL0, only one BSY interrupt will be received regardless of the num-

ber of BSY events that are generated.

Workaround: None.

Fix Plan: RevA

0K40A

Table 2. Silicon Errata (Continued)

Errata

Number

Errata Description

Applies

to Mask