Silicon Errata for the MSC8101 Processor, Mask 0K40A, Rev. 5

18

Freescale Semiconductor

CPM49

Error in FEC CAM address recognition

Date Added: 3/14/2002

Description: External CAM address recognition in Fast Ethernet controller does not function.

Workaround: Use microcode patch available from Freescale.

System Number: 5404

Fix Plan: RevA

0K40A

CPM50

MCC Transparent Super Channel Loss of Alignment

Date Added: 5/30/2000

Description: When the MCC is configured to work in Transparent, super channel first sync slot

synchronization, loss of alignment may occur when the first data (idles) on the Rx data line match-

es the value of the RCVSYNC parameter.

Workaround: Write to RCVSYNC a pattern which cannot appear in the Rx data line.

System Number: 5833

Fix Plan: Rev A

0K40A

CPM54

Error in switching to and from shadow SI ram.

Date Added: 12/10/2000, modified 15/10/2002

Description: Dynamic switching in SIRAM may not be executed properly.

Workaround: In SI RAM, when working with shadow RAM, the last entry (n) and the entry im-

mediately before the last entry (n-1) MUST have at least one common bit in the CNT or BYT

fields. For example:

SIRAM

Entry

CNTBYT

n-1

000 1

n

010 1

The above is okay

n-1

101 0

n

001 0

The above is okay

n-1

100 0

n

001 0

The above is not okay.

System Number: 6282, 6283

Fix Plan: RevA

0K40A

CPM55

Error in ATM_Transmit command.

Date Added: 12/10/2000

Description: The ATM_Transmit command does not execute correctly when used on APC pri-

ority above 4.

Workaround: None.

System Number: 6162

Fix Plan: Rev A

0K40A

Table 2. Silicon Errata (Continued)

Errata

Number

Errata Description

Applies

to Mask