Silicon Errata for the MSC8101 Processor, Mask 0K40A, Rev. 5

Freescale Semiconductor

25

QCPM2

Switched External Clocks For Timers 3,4

Date Added: 8/31/2000

Description: Internal connectivity between TIN3 and TIN4 is switched.

Workaround: To work with external clock for timer3 use TIN4, and to work with timer4 us TIN

4. Please note that for timer4 using external clock (TIN3) and TOUT4 is impossible.

System Number: 6219

Fix Plan: Rev0.1

0K40A

CPM117

False Address Compression

Date Added: 11/05/2004

Description: If there are active AAL0 channels and a CRC-10 error has been received, VP-level

address compression might have false results, which could lead to one of the following:

•

Wrong calculation of a VP pointer address

•

Cells might be falsely discarded as misinserted cells

•

Misidentification of misinserted cells (in CUAB mode) This is a statistical error, which is

conditional on the reception of AAL0 cells with a CRC-10 error. The probability of false

address compression is directly correlated with higher CPM bit rate and longer system bus

latency.

While the false address compression is possible only if there are active AAL0 channels, it may

have an impact on all AAL types. However, it cannot occur unless AAL0 cells with CRC-10 error

have been received beforehand.

Workaround: Use the microcode patch supplied by Freescale.

System Number: 17129

0K40A

CPM118

Aborted HDLC Frame Followed by a Good Frame

Date Added: 7/11/2004

Description: When an aborted HDLC frame is followed by a good frame, the receive data buffer

may contain the data of the aborted frame followed by the data of the good frame.

Workaround: Use the microcode patch provided by Freescale.

System Number: 15906

Fix Plan:

0K40A

CPM119

Ethernet Collision Occurs on the Line 125 Clocks after TX_EN Assertion

Date Added: 7/11/2004

Description: When an ethernet collision occurs on the line 125 clocks after TX_EN assertion,

late collision will be reported even though this is only 63 bytes into the frame instead of 64. When

a collision occurs 124 cycles after TX_EN assertion, no event is reported, the TxBD is not closed,

and transmission halts. Retransmission behavior is correct for collisions occurring between asser-

tion of TX_EN and 123 clocks.

Workaround: Use the microcode patch provided by Freescale.

System Number: 15908

Fix Plan:

0K40A

Table 2. Silicon Errata (Continued)

Errata

Number

Errata Description

Applies

to Mask