Silicon Errata for the MSC8101 Processor, Mask 0K40A, Rev. 5

Freescale Semiconductor

19

CPM57

AAL5 Cell Corruption.

Date Added: 1/28/2001

Description: The second part of a second cell may overwrite the second part of the first cell in

an AAL5 frame.

Workaround: Use microcode patch.

Fix Plan: Rev A

0K40A

CPM64

AAL5 RxBD[LNE] error generated if PDU length exceeds 65512 bytes

Date Added: 5/31/2001

Description: When the CPM receives an AAL5 PDU between 65512-65535 bytes (maximum

length) the CPM sets the RxBD[LNE] indicating a receive length error, however the memory

buffer contents for the PDU are correct.

Workaround: Receive AAL5 PDU less than 65512 bytes or use microcode patch.

System Number: 7025

Fix Plan: Rev A

0K40A

CPM65

SS7 Microcode in ROM does not function correctly

Date Added: 8/5/2001

Description: The SS7 microcode in ROM does not function correctly and should not be used.

Workaround: Use the Enhanced SS7 microcode package.

Fix Plan: Rev A

0K40A

CPM71

CPM does not snoop MCC buffer descriptors.

Date Added: 8/5/2001

Description: When the MCC performs a DMA read or write of the buffer descriptor, GBL is not

asserted and TC2 is always driven low.Therefore cache snooping will not be enabled for MCC

BDs, therefore BDs in memory will not match the data cache. Also the bus used for the DMA is

always the 60x, therefore if the BDs are on the local bus then the DMA consumes bandwidth on

both the 60x and Local bus.

Workaround: If GBL and/or TC2 are set in the MCC TSTATE/RSTATE parameters, use mi-

crocode patch available from Freescale which fixes the above problem. If GBL and TC2 are not

set to improve performance move the MCC BDs to the 60x bus. The microcode patch will fix both

the GBL/TC2 and the bus performance issue.

System Number: 7018

Fix Plan: Rev A

0K40A

CPM72

MCC Global Underruns

Date Added: 8/5/2001

Description: An MCC transmitter global underrun (GUN) error may result from intensive activ-

ity on FCC1 (e.g.burst of short back to back Ethernet frames).This is due to the prioritization of

the MCC transmitter relative to FCC1 receiver and transmitter as well as the MCC receiver.

Workaround: Each serial channel above can request a service at normal or emergency level. In

case of emergency, the request is handled before normal (non-emergency) request of the channels

at a higher priority level.The proposed change is to allow the MCC transmitter to assert an emer-

gency request instead of normal request. The impact on FCC1 in this case is minimal.This feature

will controlled by a new MCC mode bit in future MSC8101 revisions. This new MCC mode bit

will allow users to continue to use the current CPM priority scheme in their applications if re-

quired.

System Number:

Fix Plan: RevA

0K40A

Table 2. Silicon Errata (Continued)

Errata

Number

Errata Description

Applies

to Mask