Silicon Errata for the MSC8101 Processor, Mask 0K40A, Rev. 5

14

Freescale Semiconductor

CPM27

Error in Heartbeat Checking in FCC

Date Added: 5/30/2000

Description: The heartbeat checking in FCC transmit ethernet 10Mbps does not work properly.

The standard requires that the collision pulse from the PHY should be checked within a window

of 4usec from the falling edge of the carrier sense. The MSC8101 samples the collision signal only

once at exactly 4usec (10 serial clocks) after the falling edge of the carrier sense signal.

Workaround: None

System Number: 4155

Fix Plan: Rev A

0K40A

CPM28

Error in Receive Frame Threshold

Date Added: 5/30/2000

Description: In the SCC Rx in HDLC mode, RFTHR does not work. There is no way to get in-

terrupts on the receive side after a programmable number of frames.

Workaround: RFTHR should be programed to 1.

System Number: 4163

Fix Plan: Rev A

0K40A

CPM29

MAXD1 and MAXD2 May Not Be Less Than MFLR

Date Added: 5/30/2000

Description: In SCC Rx ethernet, the option of transferring only part of a frame into memory

(MAXD1 and MAXD2 < MFLR) does not work.

Workaround: None

System Number: 4166

Fix Plan: Rev A

0K40A

CPM30

Graceful Stop Command Does Not Work

Date Added: 5/30/2000

Description: The graceful stop command does not work in SCC Tx in the following protocols:

Ethernet, HDLC, Transparent.

Workaround: None

System Number: 4167

Fix Plan: Rev A

0K40A

CPM35

Data Corruption in SCC Transparent Mode

Date Added: 5/30/2000

Description: When SCC transparent, envelope mode is used and the received frame size is (4*n)

+ 1, the last byte is corrupted. When GSMR_H(RFW) - rx FIFO width is used, the received data

is completely corrupted, not just the last byte.

Workaround: The bug can be worked around with a microcode patch.

System Number: System number; 4350

Fix Plan: Rev A

0K40A

Table 2. Silicon Errata (Continued)

Errata

Number

Errata Description

Applies

to Mask