M58LT128GS datasheet(42/98 Pages) STMICROELECTRONICS

42 / 98 page

7 Read modes

M58LT128GST, M58LT128GSB

42/98

Read modes

Read operations can be performed in two different ways depending on the settings in the

Configuration Register. If the clock signal is ‘don’t care’ for the data output, the read operation is

asynchronous; if the data output is synchronized with clock, the read operation is synchronous.

The read mode and format of the data output are determined by the Configuration Register.

(See Configuration Register section for details). All banks support both asynchronous and

synchronous read operations.

7.1

Asynchronous Read modes

In Asynchronous Read operations the clock signal is ‘don’t care’. The device outputs the data

corresponding to the address latched, that is the memory array, Status Register, Common

Flash Interface or Electronic Signature depending on the command issued. CR15 in the

Configuration Register must be set to ‘1’ for asynchronous operations. In Asynchronous Read

mode, the WAIT signal is always deasserted.

The device features an Automatic Standby mode. During Asynchronous Read operations, after

a bus inactivity of 150ns, the device automatically switches to the Automatic Standby mode. In

this condition the power consumption is reduced to the standby value and the outputs are still

driven.

Asynchronous Read operations can be performed in two different ways, Asynchronous

Random Read and Asynchronous Page Read.

7.1.1

Asynchronous Random Read

Asynchronous Random Read operations are controlled by the Latch Enable, L, signal.

A valid bus operation involves setting the desired address on the Address Inputs, setting Chip

Enable and Latch Enable Low, VIL, and keeping Write Enable High, VIH. The address is latched

on the rising edge of Latch Enable, L, before the value is output on the data bus. Once latched,

the Address Inputs can change. Set Output Enable Low, VIL, to read the data on the Data

Inputs/Outputs.

See Table 22: Asynchronous Read AC Characteristics, and Figure 9: Asynchronous Random

Access Read AC Waveforms for details.

7.1.2

Asynchronous Page Read

Only Asynchronous Page Read takes full advantage of the internal page storage so different

timings are applied. In Asynchronous Page Read mode, a Page of data is internally read and

stored in a Page Buffer. The Page size is 8 Words and is addressed by address inputs A0, A1

and A2.

The first read operation within the Page has the normal access time (tAVQV), subsequent reads

within the same Page have much shorter access times (tAVQV1). If the Page changes then the

normal longer timings apply again.

See Table 22: Asynchronous Read AC Characteristics, Figure 10: Asynchronous Page Read

AC Waveforms for details.

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