LS1020A datasheet(11/71 Pages) FREESCALE

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LS1021A/LS1020A Overview

TWR-LS1021A Reference Manual, Rev. 0

1-2

Freescale Semiconductor

1.2

Silicon features

A LS1021A or LS1020A processor includes the following functions and features:

•

Two (LS1021A) ARM Cortex-A7 cores based on Harvard architecture including AMBA4

MPCORE™ Virtualization, each with separate ECC protected L1 32KB I Cache and 32KB D

Cache and a shared 512 KB L2 cache with ECC protection.

— Up to 1.0 GHz at 1.0 V with 32-bit ISA support

— Three levels of instructions: User, supervisor, and hypervisor

— Independent boot and reset

— Secure boot capability with QorIQ Trust Architecture and ARM TrustZone support

•

Hierarchical interconnect fabric

— Cache Coherency Interconnect (CCI-400)

•

16-/32-bit DDR3LP/DDR4 SDRAM memory controller with ECC

•

Encryption/Decryption (SEC 5.x)

•

RegEx pattern matching (PME 2)

•

VeTSEC Ethernet interfaces

— Three 1 Gbps Ethernet controllers with IEEE 1588

•

High speed peripheral interfaces

— Two PCI Express 2.0 controllers/ports running at up to 5 GHz

•

Additional peripheral interfaces

— One SATA3 controller supporting up to 6 Gb/s operation

— One USB 2.0/3.0 controller with integrated PHY, and one USB 2.0 controller with ULPI

interface

— SD/SDXC/eMMC

— Two SPI controllers and one QuadSPI controller

— Three I2C controllers

— Four 16550 compliant UARTs and 6 LPUARTs

— Integrated flash controller (IFC)

— Integrated LCD controller 2D-ACE (only on LS1021A)

— Four FlexCAN controllers (only on LS1021A)

•

Multicore programmable interrupt controller (PIC)

•

One 8-channel DMA engine

•

QUICC Engine block (LS1021A only)

— 32-bit RISC controller for flexible support of the communications peripherals

— Serial DMA channel for receive and transmit on all serial channels

— Two universal communication controllers, supporting TDM, HDLC, UART, and ISDN

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