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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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LS1020A датащи(PDF) 34 Page - Freescale Semiconductor, Inc |
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LS1020A датащи(HTML) 34 Page - Freescale Semiconductor, Inc |
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34 / 71 page  Architecture TWR-LS1021A Reference Manual, Rev. 0 Freescale Semiconductor 2-19 — Raster (framebuffer) width, height and depth — An “Area Of Interest”, often just equal to the display width and height. • Pixel clock within limits of monitor • Horizontal and vertical sync parameters, which include: — Polarity (generally positive, but not always) — Front/back “porch” - the interval between sync transitions and active pixel data; usually one or two pixel clocks (HSYNC) or one or two lines (VSYNC) is sufficient. — Sync assertion time - display width (in pixels) + front and back porch (in pixels), plus the sync assertion time, should be approximately equal to the monitor stated horizontal timing parameter (which might be in units of microseconds, pixels or Hz). A similar process is used for vertical timing. The DCU block are configured as described in Table 2-13. 2.14 I2C The LS1021A / LS1020A devices support up to four I2C buses. Figure 2-14 shows the I2C subsystem connection. The devices available on each I2C bus segment are listed in Table 2-14. Table 2-13. DIU configuration Configuration signal Controls Value Description cfg_mux_qetdm_diu0 SW: SW3[6] REG:0x0C 0 QE TDM signals are routed to the DCU block. 1 QE TDM signals are routed to the UCC block. |
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