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LS1020A датащи(PDF) 41 Page - Freescale Semiconductor, Inc

номер детали LS1020A
подробное описание детали  TWR-LS1021A Reference Manual
PDF  71 Pages
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производитель  FREESCALE [Freescale Semiconductor, Inc]
домашняя страница  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

LS1020A датащи(HTML) 41 Page - Freescale Semiconductor, Inc

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Architecture
TWR-LS1021A Reference Manual, Rev. 0
2-26
Freescale Semiconductor
2.20
JTAG port
The COP/JTAG architecture is shown in Figure 2-20.
Figure 2-20. JTAG/COP connections
JTAG commands are accepted from the standard COP/JTAG/CCS header and are sent to LS1021A. JTAG
could be accessed by external emulator or MBED.
JTAG RST connect to CPLD to generate PORESET signals only at power up.
2.21
GPIO pins
The LS1021A has no dedicated GPIO pins; instead, GPIO functions are multiplexed internally on other
signals, which must be disabled before using the GPIO functions. Because GPIO is not needed for board
operation, GPIO evaluation is strictly limited to validation purposes.
In an addition, to remain those GPIO pins primary function, CPLD registers will offer GPIO pin functions
for TWR modules control.
Table 2-18. GPIO mapping
DUT Primary
Function
DUT GPIO
Function
Notes
GPIO
GPIO_3[13]
Connect to TWR-ELEV pin A10.
GPIO
GPIO_3[14]
Connect to TWR-ELEV pin B23.
ASLEEP, RTC, etc
GPIO_1[13:26]
Required for non-GPIO function



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