LS1020A datasheet(63/71 Pages) FREESCALE

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CPLD System Controller Architecture

TWR-LS1021A Reference Manual, Rev. 0

4-6

Freescale Semiconductor

0x08

R/W

GPIO for TWR-ELEV

Bit [0]: ELEV_GPIO_B51

Bit [1]: ELEV_GPIO05_B52

Bit [2]: ELEV_GPIO22_D43

Bit [3]: ELEV_GPIO25_C9

Bit [4]: ELEV_GPIO06_A35

Bit [5]: ELEV_GPIO07_A11

Bit [6]: ELEV_GPIO04_B35

Bit [7]: ELEV_GPIO02_B22

gpio

0x00

0x09

R/W

I2C3 and IFC CS Selection Register

Bit [0]: 0 I2C3 (default)

1 IFC_CS2_B and IFC_CS3_B

Bit [7:1]: Reserved

i2c3_ifc_mux

0x00

0x0A

R/W

SPI2 and LPUART/LCD Selection Register

Bit [0]: 0 SPI2

1 LPUART1/LCD

Bit [7:1]: Reserved

mux_spi2

RCW (selected

SW3[6]-MUX_S

EL)

0x0B

R/W

CAN3 and USB2 Selection Register

Bit [0]: 0 USB2

1 CAN3 (default)

Bit [7:1]: Reserved

can3_usb2_mux 0x01

0x0C

R/W

QE and LCD Selection Register

Bit [0]: 0 LCD

1 QE

Bit [7:1]: Reserved

qe_lcd_mux

RCW (selected

SW3[6]-MUX_S

EL)

0x0D

R/W

Multiplexed pins for SerDes Lanes Register

Bit [0]: MUX_SATA_SGMII1

0 lane B to SATA

1 lane B to SGMII1a

Bit [1]: MUX_PCIE2_SGMII1

0 lane C to SGMII1b

1 MPCIE2

Bit [2]: MUX_PCIELN2_SGMII2

0 lane D to PCIE 2nd Lane

1 lane D to SGMII2

Bit [3]: MUX_SGMII1a_SGMII1b

0 SGMII1 from lane C

1 SGMII1 from lane B

Bit [7:4]: Reserved

serdes_mux

RCW (selected

SW3[6]-MUX_S

EL)

0x0E

R/W

Writing this register to reset system with

initializing the CPLD registers to default

values

Bit [0]: 0 system running(Default)

1 system reset

Bit [7:1]: Reserved

global_rst

0x00

Table 4-3. CPLD BCSR register detail map

Base Address

Offset

Access

Type

Description

Default Value

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