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LS1020A датащи(PDF) 64 Page - Freescale Semiconductor, Inc |
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LS1020A датащи(HTML) 64 Page - Freescale Semiconductor, Inc |
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64 / 71 page ![]() CPLD System Controller Architecture TWR-LS1021A Reference Manual, Rev. 0 Freescale Semiconductor 4-7 4.4 LCD FDI translator The LCD interfaces to the Tower System or HDMI Transmitter (SiI9022A) through a 24-bit RGB interface, 8-bit R, 8-bit G, and 8-bit B. Need to translate LCD signals from FDI 2-bits to 1-bit. Figure 4-3 shows the timing for LCD FDI translation. 0x0F R/W ELEV Connector EBI_CS0 select Register Bit[2:0] 001 from IFC_CS0 010 from IFC_CS2 100 from IFC_CS3 Bit[7:3] Reserved elev_cs 0x00 0x10 R LVDD level on the board Bit[0] 0 3.3V 1 2.5V Bit[7:1] Reserved lvdd_vsel SW2[6] - LVDD_VSEL 0x11 R/W CPLD override physical switches Enable Register Bit[0] NOR Flash/QSPI selection (Register 0x12 Bit[0]) output enable 0 Disable (Default) 1 Enable Bit[7:1] Reserved soft_mux_on2 0x00 0x12 R/W NOR Flash or QSPI selection Register 1 NOR Flash Bit[7:1] Reserved nor_qspi_mux SW2[5] - NOR_QSPI_SE L Bit[0] 0 QSPI Table 4-3. CPLD BCSR register detail map Base Address Offset Access Type Description Register Name Default Value |
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