LS1020A datasheet(59/71 Pages) FREESCALE

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CPLD System Controller Architecture

TWR-LS1021A Reference Manual, Rev. 0

4-2

Freescale Semiconductor

— Power on CPU VDD, GVDD, and others powers.

•

Reset signal generation and distribution. System reset features are:

— Power on reset for LS1021A, flash, PCIe, DDR, and PHY devices with initialization of all

CPLD registers to default value.

— Manual reset: System will reset and initialize all CPLD registers to default value after pressing

reset button.

— Global register reset: Set register to reset the whole system with initializing all CPLD registers

to default value.

— Local register reset: Set register to reset the whole system and reserve all CPLD registers

current value.

•

Control POR Sequence

— Configure POR signals according to external DIP switches or board request.

•

Select Multiplexed pins

— Mux I2C and IFC CS2, CS3

— Mux SPI2 and LPUART or LCD

— Mux CAN3 and USB2

— Mux QE and LCD

— Mux SerDes configurations

•IFC Bus

— Latch out address lines from mutiplexed signals and address lines.

— Read/Write CPLD BCSR registers.

— Configure address lines to ELEV local bus pins.

•

NOR Bank Selection

— Split NOR flash to two banks.

•

LCD FDI translator

— Translate 2-bit FDI signals to 1-bit FDI signals.

4.2

Reset

The reset controller manages not only asserting reset to LS1021A, but to the rest of the system as well. It

also maintains the assertion timing of the configuration drive signal (cfg_drv), which causes the CPLD to

drive configuration values onto pin-sampled nets.

The following Figure 4-2 shows the reset sequences.

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