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LS1020A датащи(PDF) 27 Page - Freescale Semiconductor, Inc

номер детали LS1020A
подробное описание детали  TWR-LS1021A Reference Manual
PDF  71 Pages
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производитель  FREESCALE [Freescale Semiconductor, Inc]
домашняя страница  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

LS1020A датащи(HTML) 27 Page - Freescale Semiconductor, Inc

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Architecture
TWR-LS1021A Reference Manual, Rev. 0
2-12
Freescale Semiconductor
2.8.2
SGMII support
TWR-LS1021A supports evaluation of the SGMII protocol for serialized Ethernet PHYs. Ethernet data is
carried over the SerDes lanes. On TWR-LS1021A, two Atheros AR8033 PHY are used to support SGMII
mode.
2.8.3
SATA support
SATA could be evaluated an on-board SATA headers. LS1021A could support SATA3.0 protocol with
maximum 6 Gbps data rate.
2.8.4
SerDes configuration and setup
The SerDes multiplexers require initialization of several CPLD register bits. CPLD attempts to preset the
values based on a DIP switch, which should be set to match the selected RCW[cfg_srds1_prtcl] field.
Software can override the presets at any time.
GND
9
10
UIM_DATA
CLKREQ#
7
8
UIM_PWR
COEX2
561.5V
COEX1
3
4
GND
WAKE#
1
2
3.3Vaux
Table 2-8. SerDes configuration
Configuration
Signal
Controls
Value
Description
none
SW: SW3[6]
REG: 0x0D
0
Lane A PCIE#1 (x1)
Lane B SGMII 1
Lane C PCIE#2 (x1)
Lane D SGMII 2
1
Lane A PCIE#1 (x1)
Lane B SATA x1
Lane C PCIE#2 (x1)
Lane D SGMII 2
0
Lane A PCIE#1 (x1)
Lane B SGMII 1
Lane C PCIE#2 (x1)
Lane D SGMII 2
1
Lane A PCIE#1 (x1)
Lane B SATA x1
Lane C PCIE#2 (x1)
Lane D SGMII 2
Table 2-7. Specific mini PCIe pinout
Signal
Pin
Pin
Signal



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