SSD1963QL9R datasheet(80/93 Pages) ETC2

номер детали	SSD1963QL9R

подробное описание детали	1215KB Embedded Display SRAM LCD Display Controller

PDF	93 Pages

Scroll/Zoom	100%

производитель	ETC2 [List of Unclassifed Manufacturers]

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80 / 93 page

Solomon Systech

Jan 2010

P 80/93

Rev 1.1

SSD1963

12 DC CHARACTERISTICS

Conditions:

Voltage referenced to VSS

VDDD, VDDPLL = 1.2V

VDDIO, VDDLCD = 3.3V

TA = 25

°C

Table 12-1 : DC Characteristics

Symbol

Parameter

Test Condition

Min

Typ

Max

Unit

PSTY

Quiescent Power

300

500

IIZ

Input leakage current

-1

IOZ

Output leakage current

-1

VOH

Output high voltage

0.8VDDIO

VOL

Output low voltage

0.2VDDIO

VIH

Input high voltage

0.8VDDIO

VDDIO + 0.5

VIL

Input low voltage

0.2VDDIO

13 AC CHARACTERISTICS

Conditions:

Voltage referenced to VSS

VDDD, VDDPLL = 1.2V

VDDIO, VDDLCD = 3.3V

TA = 25

°C

= 50pF (Bus/CPU Interface)

= 0pF (LCD Panel Interface)

13.1 Clock Timing

Table 13-1:

Clock Input Requirements for CLK (PLL-bypass)

Symbol

Parameter

Min

Max

Units

FCLK

Input Clock Frequency (CLK)

110

MHz

TCLK

Input Clock period (CLK)

1/fCLK

Table 13-2 : Clock Input Requirements for CLK

Symbol

Parameter

Min

Max

Units

FCLK

Input Clock Frequency (CLK)

2.5

MHz

TCLK

Input Clock period (CLK)

1/fCLK

Table 13-3 : Clock Input Requirements for crystal oscillator XTAL

Symbol

Parameter

Min

Max

Units

FXTAL

Input Clock Frequency

2.5

MHz

TXTAL

Input Clock period

1/fXTAL

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