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SSD1963QL9R датащи(PDF) 36 Page - List of Unclassifed Manufacturers

номер детали SSD1963QL9R
подробное описание детали  1215KB Embedded Display SRAM LCD Display Controller
PDF  93 Pages
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производитель  ETC2 [List of Unclassifed Manufacturers]
домашняя страница  
Logo ETC2 - List of Unclassifed Manufacturers

SSD1963QL9R датащи(HTML) 36 Page - List of Unclassifed Manufacturers

Back Button SSD1963QL9R Datasheet HTML 32Page - List of Unclassifed Manufacturers SSD1963QL9R Datasheet HTML 33Page - List of Unclassifed Manufacturers SSD1963QL9R Datasheet HTML 34Page - List of Unclassifed Manufacturers SSD1963QL9R Datasheet HTML 35Page - List of Unclassifed Manufacturers SSD1963QL9R Datasheet HTML 36Page - List of Unclassifed Manufacturers SSD1963QL9R Datasheet HTML 37Page - List of Unclassifed Manufacturers SSD1963QL9R Datasheet HTML 38Page - List of Unclassifed Manufacturers SSD1963QL9R Datasheet HTML 39Page - List of Unclassifed Manufacturers SSD1963QL9R Datasheet HTML 40Page - List of Unclassifed Manufacturers Next Button
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 36 / 93 page
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Solomon Systech
Jan 2010
P 36/93
Rev 1.1
SSD1963
9.22 set_tear_off
Command
0x34
Parameters
None
D/C
D7
D6
D5
D4
D3
D2
D1
D0
Hex
Command
0
0
0
1
1
0
1
0
0
34
Description
TE signal is not sent from the SSD1963 to the host processor.
9.23 set_tear_on
Command
0x35
Parameters
1
D/C
D7
D6
D5
D4
D3
D2
D1
D0
Hex
Command
0
0
0
1
1
0
1
0
1
35
Parameter 1
1
0
0
0
0
0
0
0
A0
xx
Description
TE signal is sent from the SSD1963 to the host processor at the start of VFP.
A[0] : Tearing effect line mode (POR = 0)
0
The tearing effect output line consists of V-blanking information only.
1
The tearing effect output line consists of both V-blanking and H-blanking information by
set_tear_scanline (0x44).
The TE signal shall be active low when the display panel is in Sleep mode.
9.24 set_address_mode
Command
0x36
Parameters
1
D/C
D7
D6
D5
D4
D3
D2
D1
D0
Hex
Command
0
0
0
1
1
0
1
1
0
36
Parameter 1
1
A7
A6
A5
A4
A3
A2
A1
A0
xx
Description
Set the read order from host processor to frame buffer by A[7:5] and A[3] and from frame buffer to the display panel by
A[2:0] and A[4].
A[7] : Page address order (POR = 0)
This bit controls the order that pages of data are transferred from the host processor to the SSD1963’s frame buffer.
0
Top to bottom, pages transferred from SP (Start Page) to EP (End Page).
1
Bottom to top, pages transferred from EP (End Page) to SP (Start Page).



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