SSD1963QL9R datasheet(18/93 Pages) ETC2

18 / 93 page

Solomon Systech

Jan 2010

P 18/93

Rev 1.1

SSD1963

Figure 7-1: Relationship between Tearing Effect Signal and MCU Memory Writing

In SSD1963, users can configure the TE signal to reflect the vertical non-display period only or reflect both

vertical and horizontal non-display period. With the additional horizontal non-display period information, the

MCU can control the refresh action in more accurately by counting the horizontal line scanned by the LCD

controller. Usually, a fast MCU will not need horizontal non-display period. But a slow MCU will need it to

ensure the frame buffer update process always lags behind the LCD controller.

7.2

System Clock Generation

The system clock of SSD1963 is generated by the built-in PLL. The reference clock of the PLL can come

from either the CLK pin or the external crystal oscillator. Since the CLK pin and the output of the oscillator

was connected to PLL with an “OR” gate, the unused clock must be tied to VSS.

Before the PLL output is configured as the system clock by the bit 1 of “set_pll” command 0xE0, the system

will be clocked by the reference clock. This enables the user to send the “set_pll_mn” command 0xE2 to the

PLL for frequency configuration. When the PLL frequency is configured and the PLL was enabled with the

bit 0 of “set_pll” command 0xE0, the user should still wait for 100ms for the PLL to lock. Then the PLL is

ready and can be configured as system clock with the bit 1 of “set_pll” command 0xE0.

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