SSD1963QL9R datasheet(7/93 Pages) ETC2

7 / 93 page

SSD1963

Rev 1.1

P 7/93

Jan 2010

Solomon Systech

FIGURES

FIGURE 4-1: SSD1963 BLOCK DIAGRAM ..............................................................................................................................9

FIGURE 5-1: PINOUT DIAGRAM –TFBGA (TOPVIEW).........................................................................................................10

FIGURE 5-2 : PINOUT DIAGRAM – LQFP (TOPVIEW) ...........................................................................................................11

FIGURE 7-1: RELATIONSHIP BETWEEN TEARING EFFECT SIGNAL AND MCU MEMORY WRITING........................................18

FIGURE 7-2: CLOCK CONTROL DIAGRAM ............................................................................................................................19

FIGURE 7-3: STATE DIAGRAM OF SSD1963.........................................................................................................................20

FIGURE 9-1: EXIT INVERT MODE EXAMPLE ..........................................................................................................................28

FIGURE 9-2: ENTER INVERT MODE EXAMPLE .......................................................................................................................29

FIGURE 9-3: SET COLUMN ADDRESS EXAMPLE ...................................................................................................................30

FIGURE 9-4: SET PAGE ADDRESS EXAMPLE .........................................................................................................................31

FIGURE 9-5: SET PARTIAL AREA WITH SET ADDRESS MODE 0X36 A[4] = 0........................................................................33

FIGURE 9-6: SET PARTIAL AREA WITH SET ADDRESS MODE 0X36 A[4] = 1........................................................................33

FIGURE 9-7: SET PARTIAL AREA WITH SET ADDRESS MODE 0X36 A[4] = 0........................................................................33

FIGURE 9-8: SET PARTIAL AREA WITH SET ADDRESS MODE 0X36 A[4] = 1........................................................................33

FIGURE 9-9: SET SCROLL AREA WITH SET ADDRESS MODE 0X36 A[4] = 0 .........................................................................35

FIGURE 9-10: SET SCROLL AREA WITH SET ADDRESS MODE 0X36 A[4] = 1 .......................................................................35

FIGURE 9-11: A[7] PAGE ADDRESS ORDER .........................................................................................................................37

FIGURE 9-12: A[6] COLUMN ADDRESS ORDER....................................................................................................................37

FIGURE 9-13: A[5] PAGE / COLUMN ADDRESS ORDER ........................................................................................................37

FIGURE 9-14: A[3] RGB ORDER..........................................................................................................................................38

FIGURE 9-15: A[1] FLIP HORIZONTAL .................................................................................................................................38

FIGURE 9-16: A[0] FLIP VERTICAL......................................................................................................................................39

FIGURE 9-17: SET SCROLL START WITH SET ADDRESS MODE, 0X36 A[4] = 0.....................................................................39

FIGURE 9-18: SET SCROLL START WITH SET ADDRESS MODE, 0X36 A[4] = 1.....................................................................40

FIGURE 9-19: PWM SIGNAL ................................................................................................................................................54

FIGURE 11-1: POWER-UP SEQUENCE ...................................................................................................................................79

FIGURE 13-1: PARALLEL 6800-SERIES INTERFACE TIMING DIAGRAM (USE CS# AS CLOCK)...............................................81

FIGURE 13-2: PARALLEL 6800-SERIES INTERFACE TIMING DIAGRAM (USE E AS CLOCK) ...................................................82

FIGURE 13-3: PARALLEL 8080-SERIES INTERFACE TIMING DIAGRAM (WRITE CYCLE) .......................................................83

FIGURE 13-4: PARALLEL 8080-SERIES INTERFACE TIMING DIAGRAM (READ CYCLE).........................................................84

FIGURE 13-5: GENERIC TFT PANEL TIMING........................................................................................................................85

FIGURE 13-6: SERIAL RGB INTERFACE TIMING (WITHOUT DUMMY MODE).........................................................................86

FIGURE 13-7: SERIAL RGB INTERFACE TIMING (WITH DUMMY MODE) ...............................................................................87

FIGURE 14-1 : APPLICATION CIRCUIT FOR SSD1963 (WITH DIRECT CLOCK INPUT).............................................................88

FIGURE 14-2 : APPLICATION CIRCUIT FOR SSD1963 (WITH CRYSTAL OSCILLATOR INPUT) .................................................89

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