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SSD1963QL9R датащи(PDF) 48 Page - List of Unclassifed Manufacturers

номер детали SSD1963QL9R
подробное описание детали  1215KB Embedded Display SRAM LCD Display Controller
PDF  93 Pages
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производитель  ETC2 [List of Unclassifed Manufacturers]
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SSD1963QL9R датащи(HTML) 48 Page - List of Unclassifed Manufacturers

Back Button SSD1963QL9R Datasheet HTML 44Page - List of Unclassifed Manufacturers SSD1963QL9R Datasheet HTML 45Page - List of Unclassifed Manufacturers SSD1963QL9R Datasheet HTML 46Page - List of Unclassifed Manufacturers SSD1963QL9R Datasheet HTML 47Page - List of Unclassifed Manufacturers SSD1963QL9R Datasheet HTML 48Page - List of Unclassifed Manufacturers SSD1963QL9R Datasheet HTML 49Page - List of Unclassifed Manufacturers SSD1963QL9R Datasheet HTML 50Page - List of Unclassifed Manufacturers SSD1963QL9R Datasheet HTML 51Page - List of Unclassifed Manufacturers SSD1963QL9R Datasheet HTML 52Page - List of Unclassifed Manufacturers Next Button
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 48 / 93 page
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Solomon Systech
Jan 2010
P 48/93
Rev 1.1
SSD1963
LPS[10:8] :
Set the horizontal sync pulse (LLINE) start location in pixel clock. (POR = 000)
LPS[7:0] :
Set the horizontal sync pulse width (LLINE) in start. (POR = 00000000)
Horizontal Display Period Start Position = LPS pixels
LPSPP[1:0] : Set the horizontal sync pulse subpixel start position for serial TFT interface (POR = 00)
Timing refer to Figure 13-5.
9.36 get_hori_period
Command
0xB5
Parameters
8
D/C
D7
D6
D5
D4
D3
D2
D1
D0
Hex
Command
0
1
0
1
1
0
1
0
1
B5
Parameter 1
1
0
0
0
0
0
HT10
HT9
HT8
xx
Parameter 2
1
HT7
HT6
HT5
HT4
HT3
HT2
HT1
HT0
xx
Parameter 3
1
0
0
0
0
0
HPS10
HPS9
HPS8
xx
Parameter 4
1
HPS7
HPS6
HPS5
HPS4
HPS3
HPS2
HPS1
HPS0
xx
Parameter 5
1
0
HPW6
HPW5
HPW4
HPW3
HPW2
HPW1
HPW0
xx
Parameter 6
1
0
0
0
0
0
LPS10
LPS9
LPS8
xx
Parameter 7
1
LPS7
LPS6
LPS5
LPS4
LPS3
LPS2
LPS1
LPS0
xx
Parameter 8
1
0
0
0
0
0
0
LPSPP1
LPSPP0
xx
Description
Get current front porch and back porch settings
HT[10:8] :
High byte of the horizontal total period (display + non-display) in pixel clock (POR = 010)
HT[7:0] :
Low byte of the horizontal total period (display + non-display) in pixel clock (POR = 10101111)
HPS[10:8] :
High byte of the non-display period between the start of the horizontal sync (LLINE) signal and the first
display data. (POR = 000)
HPS[7:0] :
Low byte of the non-display period between the start of the horizontal sync (LLINE) signal and the first
display data. (POR = 00100000)
HPW[6:0] :
The horizontal sync pulse width (LLINE) in pixel clock. (POR = 0000111)
LPS[10:8] :
High byte of the horizontal sync pulse (LLINE) start location in pixel clock. (POR = 000)
LPS[7:0] :
Low byte of the horizontal sync pulse width (LLINE) in start. (POR = 00000000)
LPSPP[1:0] : The horizontal sync pulse subpixel start position (POR = 00)



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