LTC4244IGN datasheet(20/28 Pages) LINER

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LTC4244/LTC4244-1

42441f

Power MOSFET Selection Criteria

The LTC4244 uses external MOSFETs to limit the 5V and

3.3V supply currents. The following criteria should be

used when selecting these MOSFET’s:

1. The on resistance should be low enough to prevent an

excessive voltage drop across the sense resistor and

the series MOSFET at rated load current given the

amount of gate to source voltage provided by the

LTC4244.

2. The drain-to-source breakdown voltage should be high

enough for the device to survive overvoltage transients

that may occur during fault conditions (the 5V and 3.3V

transient voltage limiters shown in Figure 1 will limit the

maximum drain-source voltage seen by these MOSFET’s

during fault conditions).

3. The MOSFET package must be able to handle the

maximum, steady state power dissipation for the ON

state without exceeding the device’s rated maximum

junction temperature. The MOSFET’s steady-state, dis-

sipated power can be expressed as:

PON = IMAX2 • RDS(ON)

(8)

The increase in steady-state junction-to-ambient tem-

perature is given by:

TJ – TA = PON • RθJA

(9)

4. The MOSFET package must be able to dissipate the heat

resulting from the power pulse during the transition

from off to on. A worst-case approximation for the

magnitude of the power pulse is:

OUT

INRUSH

LOAD

OFF-ON <

()

•

(10)

where

nVOUT = 5VOUT or 3.3VOUT, IINRUSH is the tran-

sient current initially charging the load capacitance and

ILOAD is the steady-state load current. The duration, tON,

of the power pulse can be expressed as:

LOAD

OUT

INRUSH

•

(11)

APPLICATIO S I FOR ATIO

5. The MOSFET package must be able to sustain the

maximum pulse power that occurs in the event the

LTC4244 attempts to power-up either the 5V or 3.3V

back-end supply into a short circuit (see Design Ex-

ample for a sample calculation).

Table 8 lists some power MOSFET’s that can be used with

the LTC4244.

Input Overvoltage Transient Protection

Hot plugging a board into a backplane generates inrush

currents from the backplane power supplies due to the

charging of the plug-in board capacitance. To reduce this

transient current to a safe level, the CPCI Hot Swap

specification restricts the amount of unswitched capaci-

tance used on the input side of the plug-in board. Each

medium or long power pin connected to the CPCI female

connector on the plug-in board is required to have a 10nF

ceramic bypass capacitor to ground. Bulk capacitors are

only allowed on the switched output side of the LTC4244

(5VOUT, 3.3VOUT, 12VOUT, VEEOUT). Some bulk capaci-

tance is allowed on the 5VIN and 3.3VIN Early Power

planes, but only because a current limiting resistor is

assumed to decouple the connector pin from the bulk

capacitance. Circuits normally placed on the unswitched

side Early Power plane (PCI Bridge, for example) need to

to be decoupled by a current limiting resistor.

Disallowing bulk capacitors on the input power pins miti-

gates the inrush current during Hot Swap. However, it also

tends to create a resonant circuit formed by the inductance

of the backplane power supply trace in series with the

inductance of the connector pin and the parasitic capaci-

tance of the plug-in board (mainly due to the large power

FET). Upon board insertion, the ringing of this circuit can

exhibit a peak overshoot of 2.5 times the steady-state

voltage (>30V for 12VIN).

There are two methods for abating the effects of these high

voltage transients: using voltage limiters to clip the tran-

sient to a safe level and snubber networks. Snubber

networks are series RC networks whose time constants

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