LTC4244IGN datasheet(7/28 Pages) LINER

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LTC4244/LTC4244-1

42441f

PI FU CTIO S

12VIN (Pin 1): 12V Supply Input. A 0.5Ω switch is con-

nected between 12VIN and 12VOUT with a foldback current

limit. An undervoltage lockout circuit prevents the switches

from turning on while the 12VIN pin voltage is less than 9V.

12VIN also provides power to the LTC4244’s internal VCC

node.

VEEIN (Pin 2): –12V Supply Input. A 1Ω switch is con-

nected between VEEIN and VEEOUT with a foldback current

limit. An undervoltage lockout circuit prevents the switches

from turning on while the VEEIN pin voltage is greater than

–9.25V. The VEEIN undervoltage lockout function is dis-

abled for the LTC4244-1.

5VOUT (Pin 3): 5V Output Sense. The PWRGD pin will not

pull low until the 5VOUT pin voltage exceeds 4.61V. A 200Ω

active pull-down discharges 5VOUT to ground when the

power switches are turned off.

TIMER (Pin 4): Current Fault Inhibit Timing Input and

Auxiliary VCC. Connect a capacitor from TIMER to GND.

When the LTC4244 is turned on, a 21

µA pull-up current

source is connected to TIMER. Current limit faults will be

ignored until the voltage at the TIMER pin rises to within

1.6V of 12VIN. After the TIMER pin has completed ramp-

ing up, the TIMER capacitor serves as an auxiliary charge

reservoir for VCC in the event the 12VIN pin voltage

momentarily drops below the undervoltage lockout thresh-

old voltage. When the LTC4244 is turned off (OFF/ON >

2V), the TIMER pin is pulled down to GND. After the TIMER

pin voltage drops to within 0.8V of GND, the TIMER latch

is reset and the part is ready for another power cycle.

OFF/ON (Pin 5): Digital Input. Connect the CPCI BD_SEL#

signal to the OFF/ON pin. When the OFF/ON pin is pulled

low, the GATE pin is pulled high by a 67

µA current source

and the internal 12V and –12V switches are turned on.

When the OFF/ON pin is pulled high, the GATE pin will be

pulled to ground by a 60

µAcurrentsourceandthe12Vand

–12V switches turn off.

FAULT (Pin 6): Open-Drain Digital I/O. FAULT is pulled low

when a current limit fault is detected. Current limit faults

are ignored until the voltage at the TIMER pin is within 1.6V

of 12VIN. Once the TIMER cycle is complete, FAULT will

pull low and the LTC4244 latches off in the event of an

overcurrent fault. The part will remain in the latched off

state until the OFF/ON pin is cycled high then low. Forcing

the FAULT pin low with an external pull-down will cause

the part to latch into the off state after a 25

µs deglitching

time.

PWRGD (Pin 7): Open-Drain Digital Power Good Output.

Connect the CPCI HEALTHY# signal to the PWRGD pin.

PWRGD remains low while V12VOUT ≥ 11.1V, V3.3VOUT ≥

2.9V, V5VOUT ≥ 4.61V, and VEEOUT ≤ –11.1V. When any of

the supplies falls below its power good threshold voltage,

PWRGD will go high after a 14

µs deglitching time.

GND (Pin 8): Device Ground.

RESETIN (Pin 9):Digital Input. Connect the CPCI PCI_RST#

signal to the RESETIN pin. Pulling the RESETIN pin low will

cause RESETOUT to pull low. RESETOUT will also pull low

when PWRGD is high.

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