LTC4244IGN datasheet(12/28 Pages) LINER

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LTC4244/LTC4244-1

42441f

•5VIN UVL Threshold Voltage: The LTC4244’s 5VIN UVL

threshold voltage is 4.25V vs. 2.5V for the LTC1644.

•VEEOUTPWRGDThresholdVoltage:TheLTC4244VEEOUT

power good threshold voltage is –11.1V vs –10.5V for

the LTC1644.

• Absolute Maximum Ratings: The LTC4244’s absolute

maximum ratings for the 12VIN and VEEIN pins are

±14.4V, respectively, vs ±13.2V for the LTC1644.

• 5V/3.3V Circuit Breakers: If a short-circuit occurs after

power-up, the LTC4244 actively limits the voltage

dropped across the external 5V and 3.3V sense resis-

tors to 150mV for 25

µs before tripping the circuit

breaker. In the event either the 5V or 3.3V sense resistor

voltage exceeds 150mV, the LTC1644 trips the circuit

breaker without delay.

• 5V/3.3V Circuit Breaker Threshold Voltage: The LTC4244

threshold voltage is 52mV

±5mV vs 55mV ±15mV for

the LTC1644.

• External Gate Voltage: After power-up, the voltage drop

from the 12VIN pin to the GATE pin is 0.6V for the

LTC4244 vs 50mV for the LTC1644.

Hot Plug Power-Up Sequence

The LTC4244 is specifically designed for hot plugging

CPCI boards. The typical application circuit is shown in

Figure 1.

CPCI Connector Pin Sequence

The staggered lengths of the CPCI male connector pins

ensure that all power supplies are physically connected to

the LTC4244 before back-end power is allowed to ramp up

(BD_SEL# asserted low). The long pins, which include 5V,

3.3.V, V(I/O) and GND, mate first. The short BD_SEL# pin

mates last. At least one long 5V power pin must be

connected to the LTC4244 in order for the PRECHARGE

voltage to be available during the insertion sequence.

The following is a typical hot insertion sequence:

1. ESD clips make contact.

2. Long power and ground pins make contact and Early

Power is established. The 1V precharge voltage be-

comes valid at this stage of insertion. Power is also

applied to the pull-up resistors connected to the FAULT,

PWRGD and OFF/ON pins. All power switches are held

off at this stage of insertion.

3. Medium length pins make contact. Both FAULT and

PWRGD continue to be pulled up high at this stage in the

hot plug sequence, and the power switches are still held

off. The 12V and –12V connector pins also make

contact at this stage. Zener clamps Z1 and Z2 plus shunt

RC snubbers R16-C5 and R15-C4 help protect the VEEIN

and 12VIN pins, respectively, from large voltage tran-

sients during hot insertion.

The signal pins also connect at this point. These include

the HEALTHY# signal (which is connected to the PWRGD

pin), the PCI_RST# signal (which is connected to the

RESETIN pin) and the I/O connector pins (which are

biased at 1V by the LTC4244’s precharge circuit).

4. Short pins make contact. The BD_SEL# signal is con-

nected to the OFF/ON pin. If the BD_SEL# signal is

grounded on the backplane, the plug-in card power-up

cycle begins immediately. System backplanes that do

not ground the BD_SEL# signal will instead have cir-

cuitry that detects when BD_SEL# makes contact with

the plug-in board. The system logic can then control the

power up process by pulling BD_SEL# low.

Power-Up Sequence

The back-end 3.3VOUT and 5VOUT power planes are iso-

lated from the 3.3VIN and 5VIN power planes by external

N-channel pass transistors Q1 and Q2, respectively. Inter-

nal pass transistors isolate the back-end 12VOUT and

VEEOUT power planes from the 12VIN and VEEIN power

planes.

APPLICATIO S I FOR ATIO

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