LTC4244IGN datasheet(13/28 Pages) LINER

13 / 28 page

LTC4244/LTC4244-1

42441f

Sense resistors R1 and R2 provide current fault detection

and R5 and C1 provide current control loop compensation

as well as ramp rate control for the GATE pin voltage.

Resistors R3 and R4 prevent high frequency oscillations

in MOSFET’s Q1 and Q2.

A power-up sequence begins when the OFF/ON pin is

pulled low (Figure 2). This enables the pass transistors to

turn on and an internal 21

µA current source is connected

to TIMER. Once the pass transistors begin to conduct

current, the supplies will start to power up. Current limit

faults are ignored while the TIMER pin voltage is ramping

up and is less than (12VIN – 1.6V). When all four supply

voltages are within tolerance, HEALTHY# will pull low and

LOCAL_PCI_RST# is free to follow PCI_RST#.

Power-Down Sequence

When the BD_SEL# signal is pulled high, a power-down

sequence begins (Figure 3).

Internal switches are connected to each of the output

voltage supply pins to discharge the bypass capacitors to

ground. The TIMER pin is immediately pulled low. The

GATE pin is pulled down by a 60

µA current source to

prevent the load currents on the 3.3V and 5V supplies from

going to zero instantaneously and glitching the power

supply voltages. When any of the output voltages dips

below its threshold, the HEALTHY# signal pulls high and

LOCAL_PCI_RST# will be asserted low.

APPLICATIO S I FOR ATIO

TIMER

10V/DIV

GATE

10V/DIV

12VOUT

10V/DIV

5VOUT

10V/DIV

3.3VOUT

10V/DIV

VEEOUT

10V/DIV

BD_SEL#

10V/DIV

HEALTHY#

10V/DIV

LCL_PCI_RST#

10V/DIV

10ms/DIV

4244 F02

Figure 2. Normal Power-Up Sequence

TIMER

10V/DIV

GATE

10V/DIV

12VOUT

10V/DIV

5VOUT

10V/DIV

3.3VOUT

10V/DIV

VEEOUT

10V/DIV

BD_SEL#

10V/DIV

HEALTHY#

10V/DIV

LCL_PCI_RST#

10V/DIV

20ms/DIV

4244 F03

Figure 3. Normal Power-Down Sequence

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