LTC4244IGN datasheet(14/28 Pages) LINER

14 / 28 page

LTC4244/LTC4244-1

42441f

Once the power-down sequence is complete, the CPCI

card may be removed from the slot. During extraction, the

precharge circuit continues to bias the bus I/O connector

pins at 1V until the long 5V and 3.3V connector pin

connections are broken.

GATE Pin Capacitor Selection

Both the load capacitance and the LTC4244’s GATE pin

capacitor (C1 in Figure 1) affect the ramp rate of the 5VOUT

and 3.3VOUT voltages. The precise relationship can be

expressed as:

or =

OUT

LIMIT(5V)

LIMIT(3.3V)

GATE

LOAD V

LOAD VOUT

LOAD

VOUT

–

()

)

(1)

whichever is slowest. The power-up time for any of the

LTC4244’s outputs where the inrush current is constrained

by that supply’s foldback current limit can be approxi-

mated as:

on VOUT

LOAD

OUT

LIMIT VOUT

LOAD VOUT

()

••

–

(2)

Where

nVOUT = 5VOUT, 3.3VOUT, 12VOUT or VEEOUT. For

example, if CLOAD=2000µF, ILIMIT(5VOUT) = 6A and

ILOAD(5VOUT) = 5A, the 5VOUT turn-on time will be less than

20ms.

If the value of C1 is large enough that it alone determines

the output voltage ramp rate, then the magnitude of the

inrush current initially charging the load capacitance is:

INRUSH

LOAD

GATE

•

(3)

The maximum power-up time for this condition can be

approximated by:

C MAX

OUT

TH MOSFET MAX

GATE MIN

()

)

()

•(

)

(4)

where VTH,MOSFET(MAX) is the maximum threshold voltage

of the external 5V or 3.3V MOSFET.

In general, the edge rate (dI/dt) at which the back-end 5V

and 3.3V supply currents are turned on can be limited by

increasing the size of C1. Applications that are sensitive to

the edge rate should characterize how varying the size of

C1 reduces dI/dt for the external MOSFET selected for a

particular design.

In the event of a short-circuit or overcurrent condition, the

LTC4244’s GATE pin can be pulled down within 2

µs since

a 1k

Ω (R5 in Figure 1) decouples C1 from the gates of the

external MOSFET’s (Q1 and Q2 in Figure 1).

TIMER Pin Capacitor Selection

During a power-up sequence, a 21

µA current source is

connected to the TIMER pin and current limit faults are

ignored until the voltage ramps to within 1.6V of 12VIN.

This feature allows the part to power up large capacitive

loads using its foldback current limit. The TIMER inhibit

period can be expressed as:

TIMER

()

•–

(5)

The timer period should be set longer than the duration of

any inrush current that exceeds the LTC4244’s foldback

current limit but yet be short enough not to exceed the

maximum, safe operating area of the external 5V and 3.3V

pass transistors in the event of a short circuit (see Design

Example). As a design aid, the TIMER period as a function

of the timing capacitor using standard values from 0.1

µF

to 0.82

µF is shown in Table 1.

APPLICATIO S I FOR ATIO

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