DP83821 datasheet(56/86 Pages) NSC

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4.0 Register Set (Continued)

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4.2.18.1 Wake on LAN

The Wake on LAN logic provides several mechanisms for

bringing the DP83821 out of a low-power state. Wake on

ARP, Wake on Broadcast, Wake on Multicast Hash and

Wake on Phy Interrupt are enabled by setting the

corresponding bit in the Wake Command/Status Register,

WCSR. Before the hardware is programmed to a low

power state, the software must write a null receive

descriptor pointer to the Receive Descriptor Pointer

the RX fifo. Please refer to the description of the RXDP

When a qualifying packet is received, the Wake on LAN

logic generates a Wake event and asserts the PMEN PCI

signal to request a Power Management state change. The

software must then bring the hardware out of low power

mode and, if the Power Management state was D3,

reinitialize Configuration Register space. A Wake interrupt

can also be generated which alerts the software that a

Wake event has occurred and a packet was received. The

software must then write a valid receive descriptor pointer

to RXDP. The incoming packet can then be transferred into

host memory for processing. Note that the wake packet is

retained for processing - this is a feature of the DP83821.

In addition to the above Wake on LAN features, DP83821

also provides Wake on Pattern Matching, Wake on DA

match and Wake on Magic Packet with SecureOn.

4.2.18.2 Wake on Pattern Matching

Wake on Pattern Matching is an extension of the Pattern

Matching feature provided by the Receive Filter Logic.

When one or more of the Wake on Pattern Match bits are

set in the WCSR, a packet will generate a wake event if it

matches the associated pattern buffer. The pattern count

and the pattern buffer memory are accessed in the same

way as in Pattern Matching for packet acceptance. The

minimum pattern count is 2 bytes and the maximum

pattern count is128 bytes for all patterns. Packets are

compared on a byte by byte basis and bytes may be

masked in pattern memory, thus allowing for don’t cares.

Please refer to the Receive Filter section for programming

examples

4.2.19 Pause Control/Status Register

The PCR register is used to control and monitor the DP83821 Pause Frame reception and transmission. The Pause

Frame reception Logic is used to accept 802.3x Pause Frames, extract the pause length value, and initiate a TX MAC

pause interval of the specified number of slot times. The Pause Frame transmission logic is used to generate and

transmit Pause Frames to cause the far-end station to pause. Pause frames can be sent by manual control or by

programmed thresholds for the RX Data and Status FIFOs. The thresholds provide a flexible method of issuing initial

pause frames based on available space falling below the thresholds, as well as sending pause frames to cancel an active

pause interval when available space rises above the upper thresholds. Note that the thresholds are based on space

available in the FIFOs rather than space used. The transmitted Pause Frame is a Mac Control frame which contains the

following data:

DA (destination address): Pause multicast address of 01-80-C2-00-00-01

SA (source address): Set to station’s address as specified in Receive Filter Perfect Match Register

Length/Type: Mac Control Frame Type (88-08)

Mac Control Opcode: Pause frame (00-01)

Pause Length field: Programmable in PAUSE_CNT when PLEN_SEL=0.

Tag: PCR

Size: 32 bits

Hard Reset: 00000000h

Offset: 0044h

Access: Read Write

Soft Reset: 00000000h

bit

tag

description

usage

PSEN

Pause Enable

Manually enables reception of 802.3x pause frames. If pause reception has

been enabled via PSEN bit (PSEN=1), setting this bit to 0 will cause any

active pause interval to be terminated. R/W

PS_MCAST

Pause on Multicast

When set to 1, this bit enables reception of 802.3x pause frames which use

the 802.3x designated multicast address in the DA (01-80-C2-00-00-01).

When this mode is enabled, the RX filter logic performs a perfect match on

the above multicast address. The pause frame will be filtered out (not

buffered to memory) unless the RX Filter logic is also programmed to

accept this address. R/W

PS_DA

Pause on DA

When set to 1, this bit enables detection of a pause frame based on a DA

match with either the perfect match register, or one of the pattern match

buffers. R/W

PS_ACT

Pause Active

This bit is set to a 1 when the TX MAC logic is actively timing a pause

interval. RO

PS_RCVD

Pause Frame Received

This bit is set to a 1 when a pause frame has been received. This bit will

remain set until cleared by a read of this register. RO, cleared on read.

unused - returns 0

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