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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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DP83821 датащи(PDF) 29 Page - National Semiconductor (TI) |
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DP83821 датащи(HTML) 29 Page - National Semiconductor (TI) |
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29 / 86 page  3.0 Functional Description (Continued) 29 www.national.com Figure 3-18 Receive Architecture with Priority Queueing With Priority Queueing, the device will transfer packets onto up to 4 Descriptor lists. The device has four descriptor pointers and associated control logic to keep track of when descriptors are available with valid packet information. The Receiver uses the user_priority field of a VLAN tag to determine the priority, based on the 802.1Q encodings based on the number of priority queues enabled. If the packet has no VLAN tag, then a priority of 0 is assumed. There is no reordering of packets while in the Receive Data FIFO. 3.13.5 Receive State Machine The receive state machine has the following states: The receive state machine manipulates the fol- lowing internal data spaces: Inputs to the receive state machine include the following events: Receive Descriptor List Current Rx Desc Ptr Software/Memory Hardware Rx Data FIFO link bufptr cmdsts cmdsts Rx DMA bufptr RxHead link Rx Desc Cache link bufptr cmdsts link bufptr cmdsts link bufptr cmdsts link bufptr cmdsts link bufptr cmdsts link bufptr cmdsts link bufptr cmdsts link bufptr cmdsts link bufptr cmdsts link bufptr cmdsts link bufptr cmdsts RXDP1 RXDP2 RXDP3 RXDP4 Q0 Q1 Q2 Q3 rxIdle The receive state machine is idle. rxDescRefr Waiting for the "refresh" transfer of the link field of a completed descriptor from the PCI bus. rxDescRead Waiting for the transfer of a descriptor from the PCI bus into the RxDescCache. rxFifoBlock Waiting for the amount of data in the RxDataFifo to reach the RxDrainThreshold or to represent a complete packet. rxFragWrite Waiting for the transfer of data from the RxDataFIFO via the PCI bus to host memory. rxDescWrite Waiting for the completion of the write of the cmdsts field of a receive descriptor. RXDP A 32-bit register that points to the current receive descriptor. CRDD An internal bit flag that is set when the current receive descriptor has been completed, and ownership has been returned to the driver. It is cleared whenever RXDP is loaded with a new value (either by the state machine, or the driver). RxDescCache An internal data space equal to the size of the maximum receive descriptor supported. descCnt Count of bytes available for storing receive data in all of the fragments described by the current descriptor. fragPtr Pointer to the next unwritten byte in the current fragment. rxPktCnt Number of packets in the rxDataFifo. Incremented by the MAC (the fill side of the FIFO). Decremented by the receive state machine as packets are processed. rxPktBytes Number of bytes in the current packet being drained from the rxDataFifo, that are in fact currently in the rxDataFifo (Note: for packets larger than the FIFO size, this number will never be greater than the FIFO size). CR:RXEN The RXEN bit in the Command Register has been set. XferDone completion of a PCI bus transfer request. |
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