DP83821 datasheet(41/86 Pages) NSC

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4.0 Register Set (Continued)

4.2.1 Command Register

This register is used for issuing commands to the DP83821. These commands are issued by setting the corresponding

bits for the function. A global software reset along with individual reset and enable/disable for transmitter and receiver are

provided here. Setting control bits to 0 has no effect, therefore there is no need for Read/modify/writes to this register.

CCh

CCSR

Clockrun Control/Status Register

R/W

D0-DCh

Reserved

E0h

TBICR

TBI Control Register

R/W

E4h

TBISR

TBI Status Register

R/W

E8h

TANAR

TBI Auto-Negotiation Advertisement Register

R/W

ECh

TANLPAR

TBI Auto-Negotiation Link Partner Ability Register

R/W

F0h

TANER

TBI Auto-Negotiation Expansion Register

R/W

F4h

TESR

TBI Extended Status Register

R/W

F8-FCh

Reserved

100-1FCh

Alias of 00-FCh (memory mapped only)

R/W

200-2FC

Config.

Registers

32-bit Read access of PCI Configuration Registers (memory mapped only)

300-3FC

Alias of 200-2FC. 32-bit Read access of PCI Configuration Registers (memory

mapped only)

Tag: CR

Size: 32 bits

Hard Reset: 00000000h

Offset: 0000h

Access: Read Write

Soft Reset: 00000000h

bit

tag

description

usage

31-17

unused

16-13

RXPRI

RX Priority Queue Select

If Receive Priority Queueing is enabled, these bits indicate which queues

should be enabled or disabled if the RXE or RXD bits are set during a write

to this register. Bit 16 corresponds to Priority Queue 3 (highest priority),

while bit 13 corresponds to Priority Queue 0 (lowest priority). Multiple

queues can be enabled or disabled on a single access. If Priority Queueing

is disabled, then these bits have no effect. These bits read back the

enabled status for the RX Priority Queues.

12-9

TXPRI

TX Priority Queue Select

If Transmit Priority Queueing is enabled, these bits indicate which queues

should be enabled or disabled if the TXE or TXD bits are set during a write

to this register. Bit 12 corresponds to Priority Queue 3 (highest priority),

while bit 9 corresponds to Priority Queue 0 (lowest priority). Multiple

queues can be enabled or disabled on a single access. If Priority Queueing

is disabled, then these bits have no effect. These bits read back the

enabled status for the TX Priority Queues.

RST

Reset

Set to 1 to force the DP83821 to a soft reset state which disables the

transmitter and receiver, reinitializes the FIFOs, and resets all affected

registers to their soft reset state. This operation implies both a TXR and a

RXR. This bit will read back a 1 during the reset operation, and be cleared

to 0 by the hardware when the reset operation is complete.

SWI

Software Interrupt

Setting this bit to a 1 forces the DP83821 to generate a hardware interrupt.

This interrupt is mask-able via the IMR.

unused

RXR

Receiver Reset

When set to a 1, this bit causes the current packet reception to be aborted,

the receive data and status FIFOs to be flushed, and the receive state

machine to enter the idle state (RXE goes to 0). This is a write-only bit and

is always read back as 0.

DP83821 датащи(PDF) 41 Page - National Semiconductor (TI)

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