DP83821 datasheet(42/86 Pages) NSC

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4.0 Register Set (Continued)

4.2.2 Configuration and Media Status Register

This register allows configuration of a variety of device and phy options, and provides phy status information.

TXR

Transmit Reset

When set to a 1, this bit causes the current transmission to be aborted, the

transmit data and status FIFOs to be flushed, and the transmit state

machine to enter the idle state (TXE goes to 0). This is a write-only bit and

is always read back as 0.

RXD

Receiver Disable

Disable the receive state machine after any current packets in progress.

When this operation has been completed the RXE bit will be cleared to 0.

This is a write-only bit and is always read back as 0. If both RXD and RXE

are set in the same write, the RXE will be ignored, and RXD will have

precedence.

RXE

Receiver Enable

When set to a 1, and the receive state machine is idle, then the receive

machine becomes active. This bit will read back as a 1 whenever the

receive state machine is active. After initial power-up, software must insure

that the receiver has completely reset before setting this bit (See

ISR:RXRCMP).

TXD

Transmit Disable

When set to a 1, halts the transmitter after the completion of the current

packet. This is a write-only bit and is always read back as 0. If both TXD

and TXE are set in the same write, the TXE will be ignored, and TXD will

have precedence.

TXE

Transmit Enable

When set to a 1, and the transmit state machine is idle, then the transmit

state machine becomes active. This bit will read back as a 1 whenever the

transmit state machine is active. After initial power-up, software must

insure that the transmitter has completely reset before setting this bit (See

ISR:TXRCMP).

Tag: CFG

Size: 32 bits

Hard Reset: 00000000h

Offset: 0004h

Access: Read Write

Soft Reset: 00000000h

bit

tag

description

usage

LNKSTS

Link Status

Link status of the external phy. Asserted when link is good. RO

30-29

SPDSTS[1:0] Speed Status

Speed status indication from the external phy. SPDSTS[1] indicates the

value of the SPEED1000 input pin. SPDSTS[0] indicates the value of the

SPEED100 input pin. The actual values will depend on the polarity of the

signalling from the physical layer device. RO

DUPSTS

Full Duplex Status

Full Duplex status from the physical layer device as indicated by the

GP1DUP input pin. Asserted when duplex mode is set or has negotiated to

FULL. De-asserted when duplex mode has been set or negotiated to HALF.

When GP1_OE is set, this shows the status of the GP1_DUP output. RO

27-25

Reserved

Reserved. RO

TBI_EN

Ten-Bit Interface Enable

This bit enables the Ten-Bit Interface for use with 1000 Mb/s fiber devices.

When this bit is set, the MODE_1000 bit should also be set. It is loaded

from EEPROM at power-up. R/W

Reserved

Reserved. Must be written as 0. R/W

MODE_1000 1000 Mb/s Mode Control

This bit will enable 1000 Mb/s mode when set. This bit is loaded from

EEPROM at power-up. R/W

Reserved

Reserved. Must be written as 0. R/W

20-18

PINT_CTL

Phy Interrupt Control

Allows phy interrupt on changes in Phy status as follows:

1xx: change in DUPSTS

x1x: change in LNKSTS

xx1: change in SPDSTS

Note that the phy interrupt mask in the IMR register must also be set.

TMRTEST

Timer Test Mode

Speeds up 100us internal timer signal to 4us.

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