DP83821 datasheet(46/86 Pages) NSC

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4.0 Register Set (Continued)

4.2.5 PCI Test Control Register

4.2.6 Interrupt Status Register

This register indicates the source of an interrupt when the INTA pin goes active. Enabling the corresponding bits in the

Interrupt Mask Register (IMR) allows bits in this register to produce an interrupt. When an interrupt is active, one or more

bits in this register are set to a “1”. The Interrupt Status Register reflects all current pending interrupts, regardless of the

state of the corresponding mask bit in the IMR. Reading the ISR clears all interrupts. Writing to the ISR has no effect.

Tag: PTSCR

Size: 32 bits

Hard Reset: 00000000h

Offset: 000Ch

Access: Read Write

Soft Reset: 00000000h

bit

tag

description

usage

31-16

Reserved

Reserved. Must be written as a 0.

Reserved

RBIST_RST

SRAM BIST Reset

Setting this bit to 1 allows the SRAM BIST engine to be reset. R/W

12-11

Reserved

RBIST_EN

SRAM BIST Enable

Setting this bit to 1 starts the SRAM BIST engine. R/W

RBIST_DONE

SRAM BIST Done

This bit is set to 1 when the SRAM BIST completes each section. RO

RBIST_RX1FAIL

RX Status FIFO BIST Fail

This bit is set to 1 if the SRAM BIST detects a failure in RX Status

FIFO SRAM. This bit is cleared only by resetting the BIST. RO

RBIST_RX0FAIL

RX Data FIFO BIST Fail

This bit is set to 1 if the SRAM BIST detects a failure in RX Data FIFO

SRAM. This bit is cleared only by resetting the BIST. RO

Reserved

RBIST_TX0FAIL

TX Data FIFO BIST Fail

This bit is set to 1 if the SRAM BIST detects a failure in TX Data FIFO

SRAM. This bit is cleared only by resetting the BIST. RO

RBIST_HFFAIL

Hash Filter BIST Fail

This bit is set to 1 if the SRAM BIST detects a failure in the hash filter

SRAM. This bit is cleared only by resetting the BIST. RO

RBIST_RXFAIL

RX Filter BIST Fail

This bit is set to 1 if the SRAM BIST detects a failure in the RX filter

SRAM. This bit is cleared only by resetting the BIST. RO

EELOAD_EN

Enable EEPROM Load

This bit is set to a 1 to manually initiate a load of configuration

information from EEPROM. A 1 is returned while the configuration

load from EEPROM is active. R/W

EEBIST_EN

Enable EEPROM BIST

This bit is set to a 1 to initiate EEPROM BIST, which verifies the

EEPROM data and checksum without reloading configuration values

to the device. A 1 is returned while the EEPROM BIST is active. R/W

EEBIST_FAIL

EE BIST Fail indication

This bit is set to a 1 upon completion of the EEPROM BIST

(EEBIST_EN returns 0) if the BIST logic encountered an invalid

checksum. RO

Tag: ISR

Size: 32 bits

Hard Reset: 00608000h

Offset: 0010h

Access: Read Only

Soft Reset: 00608000h

bit

tag

description

usage

Reserved

TXDESC3

Tx Descriptor for Priority

Queue 3

This event is signaled after a transmit descriptor with the INTR bit set in the

CMDSTS field has been updated.

TXDESC2

Tx Descriptor for Priority

Queue 2

This event is signaled after a transmit descriptor with the INTR bit set in the

CMDSTS field has been updated.

TXDESC1

Tx Descriptor for Priority

Queue 1

This event is signaled after a transmit descriptor with the INTR bit set in the

CMDSTS field has been updated.

TXDESC0

Tx Descriptor for Priority

Queue 0

This event is signaled after a transmit descriptor with the INTR bit set in the

CMDSTS field has been updated.

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