DSM2180F3 datasheet(39/63 Pages) STMICROELECTRONICS

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DSM2180F3

POWER MANAGEMENT

The device offers configurable power saving op-

tions. These options may be used individually or in

combinations, as follows:

All memory blocks in the device are built with

zero-power management technology. Zero-

power technology puts the memories into

standby mode when address/data inputs are

not changing (zero DC current). As soon as a

transition occurs on an input, the affected

memory “wakes up”, changes and latches its

outputs, then goes back to standby. The

designer does

not have to do anything special to

achieve memory standby mode when no inputs

are changing—it happens automatically.

Both PLDs (DPLD and CPLD) are also Zero-

power, but this is not the default operation. The

DSP must set a bit at run-time to achieve Zero-

power as described next.

The PMMR registers can be written by the DSP

at run-time to manage power. The device has a

Turbo bit in the PMMR0 register. This bit can be

set to turn the Turbo mode off (the default is with

Turbo mode turned on). While Turbo mode is

off, the PLDs can achieve standby current when

no PLD inputs are changing (zero DC current).

Even when inputs do change, significant power

can be saved at lower frequencies (AC current),

compared to when Turbo mode is on. When the

Turbo mode is on, there is a significant DC

current component and the AC component is

higher.

Further significant power savings can be

achieved by blocking signals that are not used

in DPLD or CPLD logic equations. The “blocking

bits” in PMMR registers can be set to logic 1 by

the DSP to block designated signals from reach-

ing both PLDs. Current consumption of the

PLDs is directly related to the composite fre-

quency of the changes on their inputs (see Fig-

ure 25), so blocking unused PLD inputs can

significantly lower PLD operating frequency and

power consumption. The DSP also has the op-

tion of blocking certain PLD input when not

needed, then letting them pass for when needed

for specific logic operations. Table 17 and Table

18 define the PMMR registers.

PSD Chip Select Input (CSI, PD2) can be used

to disable the internal memories and

csiop

registers, placing them in standby mode even if

inputs are changing. This feature does not block

any internal signals or disable the PLDs. There

is a slight penalty in memory access time when

PSD Chip Select Input (CSI, PD2) makes its

initial transition from deselected to selected.

Table 17. Power Management Mode Registers PMMR01

Note: 1. The bits of this register are cleared to zero following Power-up. Subsequent Reset (Reset) pulses do not clear the registers.

Bit 0

Not used, and should be set to zero.

Bit 1

Not used, and should be set to zero.

Bit 2

Not used, and should be set to zero.

Bit 3

PLD Turbo

0 = on PLD Turbo mode is on

1 = off PLD Turbo mode is off, saving power.

Bit 4

PLD Array clk

0 = on

CLKIN (PD1) input to the PLD AND Array is passed onto PLDs. Every change of

CLKIN (PD1) Powers-up the PLD when Turbo bit is 0.

1 = off CLKIN (PD1) input to PLD AND Array is blocked, saving power.

Bit 5

PLD MCell clk

0 = on CLKIN (PD1) input to the PLD Macrocells is passed onto PLDs.

1 = off CLKIN (PD1) input to PLD Macrocells is blocked, saving power.

Bit 6

Not used, and should be set to zero.

Bit 7

Not used, and should be set to zero.

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