DSM2180F3 datasheet(33/63 Pages) STMICROELECTRONICS

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DSM2180F3

puts, Direction Registers, and port pin input are all

connected to the Port Data Buffer (PDB).

The Port pin’s tri-state output driver enable is con-

trolled by a two input OR gate whose inputs come

from the CPLD AND Array enable product term

and the Direction Register. If the enable product

term of any of the Array outputs are not defined

and that port pin is not defined as a CPLD output

in PSDsoft ExpressTM, then the Direction Register

has sole control of the buffer that drives the port

pin.

The contents of these registers can be altered by

the DSP. The Port Data Buffer (PDB) feedback

path allows the DSP to check the contents of the

registers.

Ports B, and C have embedded IMCs. The IMCs

can be configured as registers (for sampling or de-

bouncing), as transparent latches, or direct inputs

to the PLDs. The registers and latches are clocked

by a product term from the PLD AND Array. The

outputs from the IMCs drive the PLD input bus and

can be read by the DSP. See the section entitled

“Input Macrocell”, on page 31.

Port Operating Modes

The I/O Ports have several modes of operation.

Modes are defined using PSDsoft ExpressTM, and

then runtime control from the DSP can occur using

the registers in the

csiop block. See Application

Note

AN1171 for more detail.

Table 11 summarizes which modes are available

on each port. Each of the port operating modes

are described in the following sections.

Table 11. Port Operating Modes

Note: 1. Can be multiplexed with other I/O functions.

MCU I/O Mode. In the MCU I/O mode, the DSP

uses the I/O Ports block to expand its own I/O

ports. The DSP can read I/O pins, set the direction

of I/O pins, and change the state of I/O pins by ac-

cessing the registers in the

csiop block. The csiop

found in Table 4.

The MCU I/O direction may be changed by writing

to the corresponding bit in the Direction Register,

or by the output enable product term. When the pin

is configured as an output, the content of the Data

Out Register drives the pin. When configured as

an input, the DSP can read the port input through

the Data In buffer. See Figure 19.

PLD I/O Mode. Inputs from Ports B and C to ei-

ther PLD (DPLD or CPLD) come through IMCs. In-

puts from Port D to either PLDs are routed directly

in and do not use IMCs. Outputs from the CPLD to

Port B come from the OMC group MCELLAB0-7.

Outputs from the CPLD to Port C come from OMC

group MCELLBC0-7. Outputs from the DPLD to

Port D come from the external chip select logic

block ECS0-2.

All PLD outputs may be tri-stated at the Port pins

with a control signal. This output enable control

signal can be defined by a product term from the

PLD, or by resetting the corresponding bit in the

Direction Register to 0. The corresponding bit in

the Direction Register must not be set to logic 1 by

the DSP if the pin is defined for a PLD input signal

in PSDsoft Express. The PLD I/O mode is defined

in PSDsoft Express by specifying PLD equations.

JTAG In-System Programming (ISP). Some of

the pins on Port C are based on the IEEE 1194.1

JTAG specification and is used for In-System Pro-

gramming (ISP). You can multiplex the function of

these Port C JTAG pins with other functions. ISP

is not performed very frequently in the life of the

product, so multiplexing these pin’s functions with

general purpose I/O functions gives more utility

from Port C. See the section entitled “Program-

ming In-Circuit Using JTAG ISP”, and Application

Note

AN1153.

Port Configuration Registers (PCR). Each Port

has a set of Port Configuration Registers (PCR)

used for configuration of the pins. The contents of

the registers can be accessed by the DSP through

normal read/write bus cycles of the

csiop registers

listed in Table 4.

The pins of a port are individually configurable and

each bit in the register controls its respective pin.

For example, Bit 0 in a register refers to Bit 0 of its

Port Mode

Port B

Port C

Port D

MCU I/O

Yes

PLD I/O

McellAB Outputs

McellBC Outputs

Additional Ext. CS Outputs

PLD Inputs

Yes

JTAG ISP

Yes1

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