DSM2180F3 datasheet(29/63 Pages) STMICROELECTRONICS

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DSM2180F3

element, or combinatorial logic. The multiplexer

selects between the sequential or combinatorial

logic outputs. The multiplexer output can drive a

port pin and has a feedback path to the AND Array

inputs.

The flip-flop in the Output Macrocell (OMC) block

can be configured as a D, T, JK, or SR type in PS-

Dsoft ExpressTM. The flip-flop’s clock, preset, and

clear inputs may be driven from a product term of

the AND Array. Alternatively, CLKIN (PD1) can be

used for the clock input to the flip-flop. The flip-flop

is clocked on the rising edge of CLKIN (PD1). The

preset and clear are active High inputs. Each clear

input can use up to two product terms.

Output Macrocell Allocator. Outputs of the 16

OMCs can be routed to a combination of pins on

Port B or Port D as shown in Figure 16. The OMC

output

automatically

determined

choosing pin functions in PSDsoft ExpressTM.

Routing can occur on a bit-by-bit basis, spitting

assignment between the Ports. However, one

OMC can be routed to one Port pin only, not both.

Figure 16. OMC Allocator

Table 10. Output Macrocell Port and Data Bit Assignments

Product Term Allocator. The CPLD has a Prod-

uct Term Allocator. PSDsoft ExpressTM uses the

Product Term Allocator to borrow and place prod-

uct terms from one Macrocell to another. This hap-

pens automatically in PSDsoft ExpressTM, but

understanding how allocation works will help you if

your logic design does not “fit”, in which case you

may try selecting a different pin or different OMC

where the allocation resources may differ and the

design will then fit. The following list summarizes

how product terms are allocated:

McellAB0-McellAB7 all have three native

product terms and may borrow up to six more

McellBC0-McellBC3 all have four native product

terms and may borrow up to five more

McellBC4-McellBC7 all have four native product

terms and may borrow up to six more.

AI04915

PORT C PINS

PORT B PINS

OMCs (MCELLBC)

OMCs (MCELLAB)

32 1 0

1 0

Output

Macrocell

Port

Assignment

Native Product Terms

Maximum Borrowed

Product Terms

Data Bit for Loading or

Reading

McellAB0

Port B0

McellAB1

Port B1

McellAB2

Port B2

McellAB3

Port B3

McellAB4

Port B4

McellAB5

Port B5

McellAB6

Port B6

McellAB7

Port B7

McellBC0

Port B0 or C0

McellBC1

Port B1 or C1

McellBC2

Port B or, C2

McellBC3

Port B3 orC3

McellBC4

Port B4 orC4

McellBC5

Port B5 or C5

McellBC6

Port B6 orC6

McellBC7

Port B7 orC7

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