DSM2180F3 datasheet(26/63 Pages) STMICROELECTRONICS

26 / 63 page

DSM2180F3

26/63

The DPLD performs address decoding, and gen-

erates select signals for internal and external com-

ponents, such as memory, registers, and I/O ports.

The DPLD can generates External Chip Select

(ECS0-ECS2) signals on Port D.

The CPLD can be used for logic functions, such as

loadable counters and shift registers, state ma-

chines, and encoding and decoding logic. These

logic functions can be constructed using the 16

Output Macrocells (OMC), 16 Input Macrocells

(IMC), and the AND Array.

The AND Array is used to form product terms.

These product terms are configured from the logic

definition entered in PSDsoft Express. An Input

Bus consisting of 64 signals is connected to the

PLDs. Input signals are shown in Table 9.

Turbo Bit. The PLDs in the device can minimize

power consumption by switching off when inputs

remain unchanged for an extended time of about

70 ns. Resetting the Turbo bit to 0 (Bit 3 of the

PMMR0 register) automatically places the PLDs

into standby if no inputs are changing. Turning the

Turbo mode off increases propagation delays

while reducing power consumption. Additionally,

five bits are available in the PMMR registers in

csiop to block DSP control signals from entering

the PLDs. This reduces power consumption and

can be used only when these DSP control signals

are not used in PLD logic equations. Each of the

two PLDs has unique characteristics suited for its

applications. They are described in the following

sections.

Figure 13. PLD Diagram

Input Macrocell and Input Ports

Direct Macrocell Input to MCU Data Bus

CSIOP Select

DECODE PLD

(DPLD)

PAGE

External Chip Selects to PORT D

JTAG Select

CPLD

ALLOC.

Macrocell

Alloc.

MCELLAB

MCELLBC

Direct Macrocell Access from MCU Data Bus

16 Input Macrocell

(PORT B,C)

16 Output

Macrocell

Flash Memory Selects

PORT D Inputs

to PORT B

to PORT B or C

Data

Bus

Output Macrocell Feedback

AI04900B

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