CF52012 datasheet(47/48 Pages) INTEL

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1.13. Document Revision History for Quad-Serial Configuration

(EPCQ) Devices Datasheet

Document

Version

Changes

2018.06.01

• Updated the description for tDSU parameter.

• Added data retention feature information.

• Added information about the read flag status register operation.

• Added a note to Absolute Maximum Ratings to state the maximum undershoot and overshoot for VI.

• Updated the product obsolescence note in Supported Intel EPCQ Devices table.

• Added a link to PDN1802.

Date

Version

Changes

November 2017

2017.11.06

• Updated operation code from binary to hexadecimal

value in Summary of Operation Codes table.

• Added operation code in hex value in each operation

timing diagrams.

• Updated operation timing diagrams to improve operation

code and DLCK alignment accuracy.

• Added Registers section and included read status, write

status, read non-volatile configuration, and read non-

volatile configuration registers.

• Added note stating EPCQ16, EPCQ32, EPCQ64, and

EPCQ128 are scheduled for product obsolescence.

• Added Extended Quad Input Fast Write Bytes Operation

Timing Diagram for EPCQ512/A figure.

• Added extended quad input fast write bytes operation

code for EPCQ512/A in Summary of Operation Codes

table.

• Removed ambient temperature in Absolute Maximum

Ratings.

• Added note to EPCQ512/A device is shown as EPCQ512

inIntel Quartus Prime software.

• Updated Write Operation Timing for EPCQ512/A devices.

• Updated Recommended Operating Conditions and ICC

Supply Current for EPCQ512/A devices.

• Updated capacitance is sample-tested at a 54 MHz

frequency.

May 2016

2016.05.30

• Removed instances of 'Preliminary' and notes about

pending characterization.

• Replaced EPCQ512 instances with EPCQ512/A.

• Updated ordering code for EPCQ512/A.

• Updated AS x1 and AS x4 Pin-Out Diagrams for EPCQ64,

EPCQ128, EPCQ256, and EPCQ512/A Devices figure.

• Updated Power dissipation and Joint temperature in the

Absolute Maximum Ratings table.

January 2015

2015.01.23

• Updated non-volatile configuration register operation

code.

• Added erase subsector operation.

• Added read non-volatile configuration register operation.

• Updated AS x1 dummy clock cycles for non-volatile

configuration registers.

• Updated the erase and program cycle to up to 100,000

cycles.

• Updated write non-volatile configuration register 16-bit

continued...

1. Quad-Serial Configuration (EPCQ) Devices Datasheet

CF52012 | 2018.06.01

Quad-Serial Configuration (EPCQ) Devices Datasheet

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