CF52012 datasheet(33/48 Pages) INTEL

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1.7.5. Fast Read Operation (0Bh)

When you execute the fast read operation, you first shift in the fast read operation

code, followed by a 3-byte addressing mode (A[23..0]) or a 4-byte addressing

mode (A[31..0]), and dummy clock cycle(s) with each bit being latched-in during

the rising edge of the DCLK signal. Then, the memory contents at that address is

shifted out on DATA1 with each bit being shifted out at a maximum frequency of

100 MHz during the falling edge of the DCLK signal.

Figure 11.

Fast Read Operation Timing Diagram

To access the entire EPCQ256 or EPCQ512/A memory, use 4-byte addressing mode. In the 4-byte addressing

mode, the address width is 32-bit address.

nCS

DCLK

DATA0

DATA1

nCS

DCLK

DATA0

DATA1

28 29 30 31

Operation Code (0Bh)

8 Dummy Clock Cycles

24-Bit Address

MSB

High Impedance

23 22 21

Byte1

Byte 2

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

The first byte address can be at any location. The device automatically increases the

address to the next higher address after shifting out each byte of data. Therefore, the

device can read the whole memory with a single fast read operation. When the device

reaches the highest address, the address counter restarts at 0x000000, allowing the

read sequence to continue indefinitely.

You can terminate the fast read operation by driving the nCS signal high at any time

during data output. If the fast read operation is shifted in while an erase, program, or

write cycle is in progress, the operation is not executed and does not affect the erase,

program, or write cycle in progress.

1.7.6. Extended Dual Input Fast Read Operation (BBh)

This operation is similar to the fast read operation except that the data and addresses

are shifted in and out on the DATA0 and DATA1 pins.

1. Quad-Serial Configuration (EPCQ) Devices Datasheet

CF52012 | 2018.06.01

Quad-Serial Configuration (EPCQ) Devices Datasheet

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