CF52012 datasheet(25/48 Pages) INTEL

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Status Register Content

Memory Content

TB Bit

BP3 Bit

BP2 Bit

BP1 Bit

BP0 Bit

Protected Area

Unprotected Area

Sectors (0 to 15)

Sectors (16 to 1023)

Sectors (0 to 31)

Sectors (32 to 1023)

Sectors (0 to 63)

Sectors (64 to 1023)

Sectors (0 to 127)

Sectors (128 to 1023)

Sectors (0 to 255)

Sectors (256 to 1023)

Sectors (0 to 511)

Sectors (512 to 1023)

All sectors

None

All sectors

None

All sectors

None

All sectors

None

All sectors

None

1.6.1.2. Write Status Register Operation (01h)

The write status operation does not affect the write enable latch and write in progress

bits. You can use the write status operation to set the status register block protection

and top or bottom bits. Therefore, you can implement this operation to protect certain

memory sectors. After setting the block protect bits, the protected memory sectors

are treated as read-only memory. You must execute the write enable operation before

the write status operation.

Figure 2.

Write Status Operation Timing Diagram

Operation Code (01h)

Status Register

DATA0

nCS

DCLK

DATA

High Impedance

10 11 12 13 14 15

MSB

Immediately after the nCS signal drives high, the device initiates the self-timed write

status cycle. The self-timed write status cycle usually takes 5 ms for all EPCQ devices

and is guaranteed to be less than 8 ms. For details about tWS, refer to the related

information below. You must account for this delay to ensure that the status register is

written with the desired block protect bits. Alternatively, you can check the write in

progress bit in the status register by executing the read status operation while the

self-timed write status cycle is in progress. Set the write in progress bit to 1 during

the self-timed write status cycle and 0 when it is complete.

Related Information

Write Operation Timing on page 40

The Write Operation Parameters provides more information about tWS, tES and tWB.

1. Quad-Serial Configuration (EPCQ) Devices Datasheet

CF52012 | 2018.06.01

Quad-Serial Configuration (EPCQ) Devices Datasheet

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