CF52012 datasheet(46/48 Pages) INTEL

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Nam

AS x1 Pin-Out

Diagram

AS x4 Pin-Out

Diagram

Pin Type

Description

Number

in 8-Pin

SOIC

Package

Number

in 16-

Pin SOIC

Package

Number

in 8-Pin

SOIC

Package

Number

in 16-

Pin SOIC

Package

Input

The FPGA provides the DCLK signal. This signal provides the

timing for the serial interface. The data presented on the

DATA0

pin is latched to the EPCQ device on the rising edge

of the DCLK signal. The data on the DATA pin changes after

the falling edge of the DCLK signal and is latched in to the

FPGA on the next falling edge of the DCLK signal.

VCC

Power

Connect the power pins to a 3.3-V power supply.

Ground

Ground pin.

1.12. Device Package and Ordering Code

Related Information

Packaging Specifications and Dimensions

1.12.1. Package

The EPCQ16 and EPCQ32 devices are available in 8-pin SOIC packages. The EPCQ64,

EPCQ128, EPCQ256, and EPCQ512/A devices are available in 16-pin SOIC packages.

For a 16-pin SOIC package, you can migrate vertically from EPCQ64 device to

EPCQ128, EPCQ256, or EPCQ512/A device. You can also migrate EPCQ128 device to

EPCQ256 or EPCQ512/A device, and EPCQ256 device to EPCQ512/A device.

1.12.2. Ordering Code

Table 36.

EPCQ Device Ordering Codes

Device

Ordering Code(21)

EPCQ16

EPCQ16SI8N

EPCQ32

EPCQ32SI8N

EPCQ64

EPCQ64SI16N

EPCQ128

EPCQ128SI16N

EPCQ256

EPCQ256SI16N

EPCQ512/A

EPCQ512ASI16N

(21) N indicates that the device is lead free.

1. Quad-Serial Configuration (EPCQ) Devices Datasheet

CF52012 | 2018.06.01

Quad-Serial Configuration (EPCQ) Devices Datasheet

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