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CF52012 датащи(PDF) 37 Page - Intel Corporation |
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CF52012 датащи(HTML) 37 Page - Intel Corporation |
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37 / 48 page ![]() Figure 17. Extended Quad Input Fast Write Bytes Operation Timing Diagram for EPCQ16, EPCQ32, EPCQ64, EPCQ128 and EPCQ256 To access the entire EPCQ256 memory, use 4-byte addressing mode. In the 4-byte addressing mode, the address width is 32-bit address. DATA0 nCS DATA1 Operation Code (12h) Don’t Care MSB DATA3 DATA2 Don’t Care ‘1’ Data In 2 1 3 9 10 0 DCLK 20 17 18 19 11 12 13 14 15 16 22 21 23 25 24 26 MSB MSB MSB MSB MSB 24-bit Address Data In Data In 2 1 3 4 5 6 27 20 16 12 8 0 4 4 0 4 0 4 0 4 0 4 4 0 0 4 0 2 6 6 2 6 2 6 2 6 2 6 6 2 2 6 2 1 5 5 1 5 1 5 1 5 1 5 5 1 1 5 1 21 17 13 9 22 18 14 10 23 19 15 3 7 7 3 7 3 7 3 7 3 7 7 3 3 7 3 11 7 MSB 4 6 5 7 8 Figure 18. Extended Quad Input Fast Write Bytes Operation Timing Diagram for EPCQ512/A Devices To access the entire EPCQ512/A memory, use 4-byte addressing mode. In the 4-byte addressing mode, the address width is 32-bit address. DATA0 nCS DATA1 Operation Code (38h) Don’t Care MSB DATA3 DATA2 Don’t Care ‘1’ Data In 2 1 3 9 10 0 DCLK 20 17 18 19 11 12 13 14 15 16 22 21 23 25 24 26 MSB MSB MSB MSB MSB 24-bit Address Data In Data In 2 1 3 4 5 6 27 20 16 12 8 0 4 4 0 4 0 4 0 4 0 4 4 0 0 4 0 2 6 6 2 6 2 6 2 6 2 6 6 2 2 6 2 1 5 5 1 5 1 5 1 5 1 5 5 1 1 5 1 21 17 13 9 22 18 14 10 23 19 15 3 7 7 3 7 3 7 3 7 3 7 7 3 3 7 3 11 7 MSB 4 6 5 7 8 1.7.12. Erase Bulk Operation (C7h) This operation sets all the memory bits to 1or 0xFF. Similar to the write bytes operation, you must execute the write enable operation before the erase bulk operation. You can implement the erase bulk operation by driving the nCS signal low and then shifting in the erase bulk operation code on the DATA0 pin. The nCS signal must be driven high after the eighth bit of the erase bulk operation code has been latched in. 1. Quad-Serial Configuration (EPCQ) Devices Datasheet CF52012 | 2018.06.01 Quad-Serial Configuration (EPCQ) Devices Datasheet 37 |
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