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DLP4710

DLPS125 – NOVEMBER 2018

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Copyright © 2018, Texas Instruments Incorporated

(1)

The DMD is designed to conduct absorbed and dissipated heat to the back of the package. The cooling system must be capable of

maintaining the package within the temperature range specified in the Recommended Operating Conditions. The total heat load on the

DMD is largely driven by the incident light absorbed by the active area; although other contributions include light energy absorbed by the

window aperture and electrical power dissipation of the array. Optical systems should be designed to minimize the light energy falling

outside the window clear aperture since any additional thermal load in this area can significantly degrade the reliability of the device.

6.5 Thermal Information

DLP4710

UNIT

FQL (LGA)

100 PINS

Thermal resistance

1.1

°C/W

(1)

Device electrical characteristics are over Recommended Operating Conditions unless otherwise noted.

(2)

All voltage values are with respect to the ground pins (VSS).

(3)

To prevent excess current, the supply voltage delta |VDDI – VDD| must be less than specified limit.

(4)

Supply power dissipation based on non–compressed commands and data.

(5)

To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than specified limit.

(6)

Supply power dissipation based on 3 global resets in 200 µs.

(7)

The following power supplies are all required to operate the DMD: VDD, VDDI, VOFFSET, VBIAS, VRESET. All VSS connections are

also required.

(8)

LPSDR specifications are for pins LS_CLK and LS_WDATA.

(9)

Low-speed interface is LPSDR and adheres to the Electrical Characteristics and AC/DC Operating Conditions table in JEDEC Standard

No. 209B, Low-Power Double Data Rate (LPDDR) JESD209B.

6.6 Electrical Characteristics

Over operating free-air temperature range (unless otherwise noted)

(1)

PARAMETER

MIN

TYP

MAX

UNIT

CURRENT

260

mA

180

62

mA

40

7.4

mA

6.3

VBIAS = 18.5 V

1.1

mA

VBIAS = 18 V

0.9

VRESET = –14.5 V

5.4

mA

VRESET = –14 V

4.4

(4)

VDD = 1.95 V

507

mW

VDD = 1.8 V

324

(4)

VDDI = 1.95 V

120.9

mW

VDD = 1.8 V

72

Supply power dissipation:

VOFFSET = 10.5 V

77.7

mW

VOFFSET = 10 V

63

Supply power dissipation:

VBIAS = 18.5 V

20.35

mW

VBIAS = 18 V

16.2

Supply power dissipation:

VRESET = –14.5 V

78.3

mW

VRESET = –14 V

61.6

Supply power dissipation: Total

536.8

804.25

mW

0.7 × VDD

VDD + 0.3

V

–0.3

0.3 × VDD

V

0.8 × VDD

VDD + 0.3

V

–0.3

0.2 × VDD

V

Figure 10

0.1 × VDD

0.4 × VDD

V