9

DLP4710

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DLPS125 – NOVEMBER 2018

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Copyright © 2018, Texas Instruments Incorporated

(1)

The average over time (including storage and operating) that the device is not in the elevated dew point temperature range.

(2)

Exposure to dew point temperatures in the elevated range during storage and operation should be limited to less than a total cumulative

6.2 Storage Conditions

applicable for the DMD as a component or non-operational in a system

MIN

MAX

UNIT

DMD storage temperature

–40

85

°C

24

°C

28

36

°C

Cumulative time in elevated dew point temperature range

6

Months

(1)

JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process.

6.3 ESD Ratings

VALUE

UNIT

Electrostatic discharge

±2000

V

(1)

The following power supplies are all required to operate the DMD: VDD, VDDI, VOFFSET, VBIAS, and VRESET. All VSS connections

are also required.

(2)

Recommended Operating Conditions are applicable after the DMD is installed in the final product.

(3)

The functional performance of the device specified in this data sheet is achieved when operating the device within the limits defined by

the Recommended Operating Conditions. No level of performance is implied when operating the device above or below the

Recommended Operating Conditions limits.

(4)

All voltage values are with respect to the ground pins (VSS).

(5)

VOFFSET supply transients must fall within specified max voltages.

(6)

To prevent excess current, the supply voltage delta |VDDI – VDD| must be less than specified limit.

(7)

To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than specified limit.

(8)

To prevent excess current, the supply voltage delta |VBIAS – VRESET| must be less than specified limit.

(9)

LS_CLK must run as specified to ensure internal DMD timing for reset waveform commands.

(10) Refer to the SubLVDS timing requirements in .

6.4 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)

(1) (2) (3)

MIN

NOM

MAX

UNIT

Supply voltage for LVCMOS core logic

Supply voltage for LPSDR low-speed interface

1.7

1.8

1.95

V

Supply voltage for SubLVDS receivers

1.7

1.8

1.95

V

9.5

10

10.5

V

Supply voltage for mirror electrode

17.5

18

18.5

V

Supply voltage for micromirror electrode

–14.5

–14

–13.5

V

0.3

V

10.5

V

33

V

CLOCK FREQUENCY

108

120

MHz

300

540

MHz

Duty cycle distortion DCLK

44%

56%

SubLVDS input differential voltage (absolute value) Figure 8, Figure 9

150

250

350

mV

Common mode voltage Figure 8, Figure 9

700

900

1100

mV

SubLVDS voltage Figure 8, Figure 9

575

1225

mV

Line differential impedance (PWB/trace)

90

100

110

Ω

Internal differential termination resistance Figure 10

80

100

120

Ω

100-Ω differential PCB trace

6.35

152.4

mm