AD9528BCPZ datasheet(27/67 Pages) AD

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Data Sheet

AD9528

Rev. D | Page 27 of 67

PLL1 Input Dividers

Each reference input has a dedicated reference divider block.

The input dividers provide division of the reference frequency

in integer steps from 1 to 1023.

VCXO Input

The VCXO receiver provides the low phase noise oscillator

input for PLL1. This signal is also the reference input for PLL2.

In addition, the VCXO input is used when either PLL1 is

bypassed, or PLL1 and PL2 are bypassed to use the AD9528 as

a buffer.

PLL1 Reference Switchover

The reference monitor verifies the presence or absence of the

REFA and REFB signals. The status of the reference monitor

guides the activity of the switchover control logic. The AD9528

supports automatic and manual PLL reference clock switching

between REFA (the REFA and REFA pins) and REFB (the REFB

and REFB pins).

There are several configurable modes of reference switchover.

The manual switchover is achieved either via programming a

selecting REFB, REFB must be present prior to when the

switchover to REFB occurs. The automatic switchover occurs

when REFA disappears and a reference is on REFB. PLL1

operates with REFA as the primary reference input; this is

relevant to the switchover operation of the device.

The reference switchover circuitry recognizes that REFA is the

master reference. For the reference monitoring circuitry to work

properly, REFA must be present during initial locking, regardless

of whether REFB is present or not. When both references are

used, REFA and REFB must be present. When a single reference

is used, the reference must be REFA.

The reference automatic switchover can be set to work as

follows:

•

Nonrevertive. Stay on REFB. Switch from REFA to REFB

when REFA disappears, but do not switch back to REFA if

it reappears. If REFB disappears, then go back to REFA.

•

Revert to REFA. Switch from REFA to REFB when REFA

disappears. Return to REFA from REFB when REFA

returns.

If a switchover event occurs in nonrevertive mode and the

missing input to REFA is reestablished, the return of the

missing reference does not reset the nonrevertive switchover

logic. The result of this setup is that, if REFB is selected during

nonrevertive switchover mode and nonrevertive switchover is

disabled and reenabled, REFB is still the active reference,

regardless if REFA is present. The switchover logic can be reset

by issuing a device reset.

PLL1 Holdover

In the absence of both input references, the device enters

holdover mode. When the device switches to holdover mode,

the charge pump tristates, allowing VCXO_VT to maintain its

existing value for a period of time. Optionally, the charge pump

can be programmed to force VCXO_VT to VDD/2. The device

continues operating in this mode until a reference signal

becomes available. Then the device exits holdover mode, and

PLL1 resynchronizes with the active reference. Automatic

holdover mode can be disabled with a register bit. PLL2 remains

locked to the VCXO signal even when PLL1 is in holdover.

PLL1 Lock Time

The typical PLL1 lock time occurs within 5× the period of the

loop bandwidth, assuming a third-order loop filter with a phase

margin of 55°. It may take up to 10× the period of the loop

bandwidth for the PLL1 lock detector circuit to show locked

status.

Calculate PLL1_TO in Figure 52 as

PLL1_TO = 10/LBWPLL1

where:

PLL1_TO is the PLL1 timeout.

LBWPLL1 is the loop bandwidth of PLL1.

COMPONENT BLOCKS—PLL2

PLL2 General Description

PLL2 consists of an optional input reference 2× multiplier,

reference divider, a PFD, a mostly integrated analog loop filter,

an integrated voltage controlled oscillator (VCO), and a feedback

divider. The VCO produces a nominal 3.8 GHz signal with an

output divider that is capable of division ratios of 3, 4, and 5.

PLL2 has a VCO with multiple bands spanning a range of

3.450 GHz to 4.025 GHz. The device automatically selects the

appropriate band as part of its calibration process.

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